DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, Species 2 (drawn to claims 1-8) in the reply filed on 30 July 2026 is acknowledged. The traversal is on the grounds that the features of the Species presented in the Restriction/Election Requirement are not mutually exclusive. This is found persuasive, thus the election between the Species is withdrawn. However, the Restriction requirement between the product and method inventions Group I and Group II is still deemed proper, and Applicant has not presented arguments regarding any errors in the Restriction requirement between Group I and Group II, or reasons for traversal of the Restriction requirement between Group I and Group II.
The Restriction Requirement is made final.
Claims 9-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Claims 1-8 are examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (“Park” US 2023/0389289) and Vega et al. (“Vega” US 2022/0209018) as evidenced by Lu (US 2024/0298439).
Regarding claim 1, Park teaches a memory device (Figures 1-4) comprising:
a memory array region (cell region, para. [0090]) on a memory die, the memory array region having an array of memory cells (para. [0090], Figures 1-4);
a periphery to the memory array region on the memory die (see para. [0090], describes a peripheral circuit region).
a metal shield (shield patterns 400, lower portions, Figures 1-4, see para. [0092]) integrated in the memory array region (see Figures 1-4), the metal shield (400) being a shield to digit lines (bit lines, para. [0047]) of the array.
Park does not explicitly teach an FDSOI CMOS device in the peripheral region.
Vega teaches a fully depleted silicon-on-insulator (FDSOI) complementary metal-oxide-semiconductor (CMOS) device (para. [0031], Figures 1-3, para. [0022] also describes the FDSOI CMOS may be used in logic or memory devices, thus can be integrated in a peripheral region of a memory die); and
a metal body plate (180/190) arranged as a back gate to the FDSOI CMOS device (para. [0042]-[0043]).
It would have been obvious to a person having ordinary skill in the art to incorporate the FDSOI CMOS transistor of Vega into the peripheral regions of the memory device of Park for the purpose of reducing current leakage as evidenced by Lu (para. [0002]).
Regarding claim 2, Park teaches wherein the digit lines (bit line structures, conductive patterns, para. [0045]) are metal digit lines (see para. [0045]).
Regarding claim 3, Park teaches wherein the memory array region (Figures 1-4) includes metal shield lines (400, upper portions between the bit line conductive patterns in Figures 1-4) between adjacent digit lines (bit line conductive patterns) in the memory array region (see Figures 1-4, para. [0047]).
Regarding claim 4, Park teaches wherein the metal shield lines (400, upper portions) extend vertically from the metal shield (400, lower portions) in the memory array region (see Figures 1-4, the upper portion of the shield patterns 400 extends vertically from the lower portion of the shield patterns 400, the metal shield).
Regarding claim 5, Vega teaches wherein channels (240/250) of the FDSOI CMOS device are separated from the metal body plate (180/190) in the periphery by a buried oxide (150, see Figure 3, para. [0038]).
Regarding claim 6, Vega teaches wherein the metal body plate (180/190) includes a first body plate (180) separated from a second body plate (190) by an insulating dielectric region (170, see Figure 3).
Regarding claim 7, the combination of Park and Vega teaches wherein the metal body plate (180/190 of Vega) and the metal shield (400, lower portion of Park) have a common composition (both have metallic, electrically conductive compositions, see para. [0050] of Park and para. [0044] of Vega).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Park, Vega, and Lu as applied to claim 1 above, and further in view of Burns, Jr. et al. (“Burns” US Patent No. 6,013,548).
Regarding claim 8, Park does not explicitly teach wherein the array of memory cells has a 4F2 cell configuration.
Burns teaches an array of memory cells having a 4F2 cell configuration (Burns, abstract).
It would have been obvious to a person having ordinary skill in the art to use the 4F2 cell configuration as taught by Burns in the memory device of Park for the purpose of reducing word line capacitance (Burns, col. 30 line 66 – col. 31 line 6).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
