DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-10, 12-15 are rejected under 35 U.S.C. 102 as being anticipated by Wang et. al., (US 2021/0013839 A1).
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Fig. 1 of Li annotated by the examiner for ease of reference.
Regarding claims 1 and 10, Wang teaches (i.e. in Fig. 2) A Doherty amplifier circuit (200, §0028), comprising:
a main amplifier (220, §0029) section.
a peaking amplifier (230, §0030) section, an output of the peaking amplifier section connected to an output (250) of the main amplifier (220) section at a combining node (260) in the Doherty amplifier circuit (200); and
a direct current (DC) blocking capacitor (Cblk) connected between the combining node (260) and an output (ZL) of the Doherty amplifier circuit (200).
Further per claim 10, a DC blocking capacitor (Cblk) connected in series in the transmit signal path (§0002-§0003) and shared (because Cblk is placed after the combining node (260)) by the main (220) and peaking (230) amplifier circuits.
Regarding claims 4 and 14, Wang teaches the Doherty amplifier circuit according to claims 1 and 10, further comprising an impedance matching network (1st output match network 221, TLIN1, Fig. 2) connected between the output of the main amplifier section (220) and the combining node (260).
Regarding claim 5, Wang teaches the Doherty amplifier circuit according to claim 4, wherein the impedance matching network (221, TLIN1) comprises: an inductor connected between the output of the main amplifier section (220) and the combining node (260) (TLIN1, Fig. 2); and a shunt capacitor connected between the combining node (260) and ground (Cbp, Fig. 2).
Regarding claim 6, Wang teaches the Doherty amplifier circuit according to claim 1, further comprising an impedance matching network (2nd output match network 231, TLIN2, Fig. 2) connected between the output of the peaking amplifier section (230) and the combining node (260).
Regarding claim 7, Wang teaches the Doherty amplifier circuit according to claim 6, wherein the impedance matching network (231, TLIN2) comprises: an inductor connected between the output of the peaking amplifier section (230) and the combining node (260) (TLIN2, Fig. 2); and a shunt capacitor connected between the combining node (260) and ground (Cbp, Fig. 2).
Regarding claims 8 and 12, Wang teaches the Doherty amplifier circuit according to claims 1 and 10, wherein the main amplifier section (220) comprises: a metal-oxide semiconductor field-effect transistor (MOSFET, §0007, §0008) including a first source/drain coupled to the combining node (260), and a second source/drain coupled to ground (Fig. 2); and a transmission line (TLIN1) coupled between the first source/drain of the MOSFET and the combining node (260), the transmission line (TLIN1) configured to have an electrical length of about 90 degrees (λ/4, Fig. 2, §0035), as measured from the first source/drain of the MOSFET to the combining node (260).
Regarding claims 9 and 13, Wang teaches the Doherty amplifier circuit according to claims 1 and 10, wherein the peaking amplifier section (230) comprises: a metal-oxide semiconductor field-effect transistor (MOSFET, §0007, §0008) including a first source/drain coupled to the combining node (260), and a second source/drain coupled to ground (Fig. 2); and a transmission line (TLIN2, TLIN4) coupled between the first source/drain of the MOSFET and the combining node (260), the transmission line configured to have an electrical length of about 180 degrees (TLIN2 + TLIN4 being two λ/4 lines, Fig. 2, §0035, §0043), as measured from the first source/drain of the MOSFET to the combining node (260).
Regarding claim 15, Wang teaches the Doherty amplifier circuit according to claim 10, wherein the DC blocking capacitor (Cblk, Fig. 2) is configured to maximize a capacitance value and minimize an equivalent series inductance value, and to have a resonance in a higher RF frequency band (Broadband Impedance Transformer 270, Cblk, Fig. 2, §0015, §0048).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of common baseband and RF decoupling circuits for RF power amplifier at DC supply feed exemplary shown for 30W BLF245 Phillips RF MOSFET device.
Regarding claims 2 and 11, Wang teaches (i.e. in Fig. 2) all limitations of claims 1 and 10, and Wang further teaches that at least one of the main amplifier section (220, §0029) and the peaking amplifier section (230, §0030) comprises: a metal-oxide semiconductor field-effect transistor (MOSFET, §0007, §0008, §0062) including a first source/drain coupled to the combining node (260), a second source/drain coupled to ground (Fig. 2), and a gate adapted to receive an input signal (211, 212) supplied to the Doherty amplifier circuit (200);
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Wang, although doesn’t show explicitly the detail of the matching network, it is well known in the art of baseband and RF decoupling circuits for RF power amplifier at DC feed that a first and second matching inductors (L2 and L1) connected together between the first source/drain of the MOSFET (Q1=BLF245) and a second node (28 V supply node in the Fig. ); with a first decoupling capacitor (C8=1 nF) connected between a third node (the junction between L2 and L1) coupling the first (L2) and second (L1) matching inductors and ground, the first decoupling capacitor configured to shunt radio frequency (RF) signals (well known that nF range capacitors decouples RF) present at the third node (the junction between L2 and L1); a second decoupling capacitor (C2=4.7uF electrolytic) connected between the second node (28V supply node) and ground, the second decoupling capacitor (C2) configured to shunt baseband signals (well known that uF range electrolytic capacitors are for baseband decoupling) present at the second node (28V supply node).
It would have been obvious to a person having ordinary skill in the art (POSITA) before the effective filing of the invention was made to modify the Doherty amplifier circuit of Wang by incorporating the specific DC supply feed decoupling network—comprising first and second series-connected inductors along with intermediate RF and terminal baseband decoupling capacitors—as disclosed by Phillips (BLF245 circuit diagram) into the DC bias/supply feed network connected to the drain (first source/drain) of the main and/or peaking MOSFET amplifier sections of Wang.
One of ordinary skill in the art would have been motivated to modify Wang in view of Phillips because providing a multi-stage LC decoupling architecture utilizing cascading inductors and varied capacitor values (a smaller RF-shunting capacitor at an intermediate node and a larger electrolytic baseband-shunting capacitor at the supply node) effectively isolates the DC supply line from both high-frequency RF leakage and low-frequency baseband/envelope modulation signal components. Implementing this well-known decoupling structure prevents unwanted RF feedback, mitigates baseband memory effects, and improves overall power amplifier stability and efficiency, as standard in RF power amplifier DC bias circuit design.
Regarding claim 3, Wang teaches the Doherty amplifier circuit according to claim 2, wherein each of at least a subset of the first and second decoupling capacitors (Cbp) and the DC blocking capacitor (Cblk) comprises a multilayer ceramic capacitor (MLCC) (Cbp, Cblk, Fig. 2, §0040, §0048).
Claim 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Lin et al. (A 10W Fully-Integrated LDMOS MMIC Doherty in LGA Package for 2.7 GHz Small Cell Application, 2019 IEEE/MTT-S International Microwave Symposium).
Regarding claim 16, Wang teaches (i.e. in Fig. 2) A Doherty amplifier circuit (200, §0028), comprising:
a main amplifier (220, §0029) stage having an input (211) coupled to an input port (210) of the Doherty amplifier circuit (200) adapted to receive an applied radio frequency (RF) signal (RF Input);
a peaking amplifier (220, §0030) stage having an input (212) coupled to the input port (210) of the Doherty amplifier circuit (200) and having an output (260) coupled to an output (250) of the main amplifier (220) stage at a combining node (260) in the Doherty amplifier circuit (200); and
a series capacitor (Cblk) connected between the combining node (260) and an output port (ZL) of the Doherty amplifier circuit (200),
Wang, however, is not explicit about the functional limitation of having a video bandwidth characteristic that is agnostic with respect to a capacitance value of the series capacitor.
In a similar filed of endeavor, Lin teaches, in a Doherty amplifier, optimization of VBW (Video bandwidth) by carefully adding one inshin inductance Linshin and a DC bypass cap (like that of Wang) which could make a parallel inductance with the trace line including the bonding wire, combiner inductance L and choke inductance Lc2. These two parallel inductances make the total equivalent inductance smaller which results a farther VBW resonance. Since the resonance is independent of the DC by pass capacitor, Lin teaches a video bandwidth characteristic that is agnostic with respect to a capacitance value of the series capacitor.
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Fig. 1 of Lin of the two-stage LDMOS MMIC Doherty PA module.
Since VBW improvement is critical (as a teaching reference, please see Boonton’s application note, entitled, “Why are Video Bandwidth and Rise Time Important”, attached with this office action) for amplifying distortion free digital broad band signals of modern wireless communications (both Wang and Lin amplifiers are used in 3G-5G wireless RF signals modulated with wideband digital baseband signal applications), a person of ordinary skill in the art would find it obvious before the effective filing date of the invention to adding the optimum inshin inductance Linshin with DC blocking cap of Wang to improve VBW performance of the Doherty amplifier, which in turn will be independent of the capacitance value of series DC blocking capacitor as recited in claim 16 of the current invention. The modified improved VBW combination of Wang in view of Lin, thereby teaching all limitations of claim 16.
Regarding claim 17, Wang in view of Lin teaches the Doherty amplifier circuit according to claim 16, further comprising an impedance matching network (1st output match network 221, TLIN1 of Wang, Fig. 2; Output Match of Lin, Fig. 1) connected between the output of the main amplifier stage (220 of Wang; Carrier final stage of Lin, Fig. 1) and the combining node (260 of Wang; RFout node of Lin, Fig. 1).
Regarding claim 18, Wang in view of Lin teaches the Doherty amplifier circuit according to claim 16, wherein the main amplifier stage (220 of Wang, Carrier stage of Lin) comprises: a metal-oxide semiconductor field-effect transistor (MOSFET, §0007 of Wang; LDMOS MMIC Die of Lin, Fig. 1) including a first source/drain coupled to the combining node (260 of Wang; RFout node of Lin), and a second source/drain coupled to ground (Fig. 2 of Wang; Fig. 1 of Lin); and a transmission line (TLIN1 of Wang, Fig. 2; combiner line/inductance L of Lin, Fig. 1) coupled between the first source/drain of the MOSFET and the combining node (260 of Wang), the transmission line configured to have an electrical length of about 90 degrees (λ/4 line TLIN1 in Wang, Fig. 2; 90 degrees phase shift combiner in Lin, Section II-B), as measured from the first source/drain of the MOSFET to the combining node.
Regarding claim 19, Wang in view of Lin teaches the Doherty amplifier circuit according to claim 16, wherein the peaking amplifier stage (230 of Wang, Peak stage of Lin) comprises: a metal-oxide semiconductor field-effect transistor (MOSFET, §0008 of Wang; LDMOS MMIC Die of Lin, Fig. 1) including a first source/drain coupled to the combining node (260 of Wang; RFout node of Lin), and a second source/drain coupled to ground (Fig. 2 of Wang; Fig. 1 of Lin); and a transmission line (TLIN2, TLIN4 of Wang, Fig. 2; output combiner path of Lin, Fig. 1) coupled between the first source/drain of the MOSFET and the combining node (260 of Wang), the transmission line configured to have an electrical length of about 180 degrees (TLIN2 + TLIN4 being two λ/4 lines in Wang, Fig. 2; Section II-B of Lin), as measured from the first source/drain of the MOSFET to the combining node.
Regarding claim 20, Wang in view of Lin teaches the Doherty amplifier circuit according to claim 15 (as referenced via claim 16), wherein the series capacitor (Cblk of Wang, Fig. 2; DC bypass/series cap of Lin, Fig. 1) is configured to maximize a capacitance value thereof, to minimize an equivalent series inductance value, and to have a resonance at a frequency of greater than about 3.5 GHz (Lin, Section II-B, Section III, Fig. 4, showing unconditional stability and wideband response up to 5 GHz with VBW resonance optimization). It would have been obvious to a person having ordinary skill in the art before the effective filing date to optimize the series capacitor dimensions and resonance characteristics to exceed 3.5 GHz to prevent unwanted low-frequency/high-frequency resonances and maximize video bandwidth for broadband signals as taught by Lin (Section II-B).
Conclusion
The prior art, McLaren et al. (US 10,177,714B1), Bouisse (US2011/0031571 A1), Bouisse (US 2020/0382069 A1) and Bouisse (EP 3 142 252 A1) made of record and not relied upon is considered pertinent to applicant's disclosure. All the aforementioned prior arts detailed a Doherty amplifier or RF amplifier with broadband VBW performance optimized by appropriate series/shunt capacitors at strategic locations in the circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached on (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
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