DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species A in the reply filed on September 08, 2026, is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on September 08, 2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et. al. (US 20180366437 A1), hereinafter Chen, in view of Choo et. al. (US 20240096742 A1), hereinafter Choo, in further view of WaferPro (“Glass Wafer vs Silicon Wafer: An In-Depth Comparison” January 15, 2024, https://waferpro.com/glass-wafer-vs-silicon-wafer-an-in-depth-comparison/), hereinafter WaferPro.
Regarding claim 1, Chen teaches an electronic module (Fig 11 package 78, [0047]) comprising: a microchannel cooler (Fig 12 substrate 12 and not shown pipe assembly, [0052]) comprising a microchannel chip (Fig 12 substrate 12, [0018]); a plurality of functional semiconductor chips (Fig 12 package component 20A and 20B, [0019]) located face up on a second side (Fig 12 top side) of the microchannel chip (Fig 12 substrate 12, [0018]), wherein the second side (Fig 12 top side) is opposite the first side and each semiconductor chip (Fig 12 package component 20A and 20B, [0019]) of the plurality of functional semiconductor chips (Fig 12 package component 20A and 20B, [0019]) is coefficient of thermal expansion (CTE) matched to the microchannel cooler (Fig 12 substrate 12 and not shown pipe assembly, [0052]); and a first redistribution layer (RDL) containing structure (Fig 12 RDLs, [0039]) located above (Fig 12 top side) and in electrical contact (Fig 12 connected with vias 44, [0032]) with the plurality of functional semiconductor chips (Fig 12 package component 20A and 20B, [0019]), wherein the first RDL containing structure (Fig 12 RDLs, [0039]) is CTE mismatched (the dielectric material of the RDL containing structure is made of materials that are not silicon; thus the CTEs would be mismatched to that of silicon, [0035]) to each of the functional semiconductor chips (Fig 12 package component 20A and 20B, [0019]).
Chen fails to teach a glass manifold.
However, Choo teaches a glass manifold (Fig 1 manifold 126, [0025]; Figs 14A, 14B, and 14C manifold assembly is made of glass, [0088]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen to incorporate the teachings of Choo by having a glass manifold. This would provide a means of circulating a cooling liquid through microchannels ([0005] and [0006]). Examiner notes that Chen teaches that pipes are connected to the microchannels to conduct coolant (Chen: [0052]) but is silent on material and the structure to conduct the coolant.
Regarding the CTE match of the semiconductor chips to the microchannel cooler. Chen teaches the microchannel chip is made of silicon or glass ([0012]) and the semiconductor chips area made of silicon ([0020]). WaferPro teaches the CTE of silicon and glass can have an overlap and differences in CTEs can cause mechanical stress (Thermal Expansion Coefficients). One having ordinary skill in the art before the effective filing date of the claimed invention would be motivated to reduce the mechanical stress between the substrate and semiconductor chips that are closely connected. Thus, the CTEs would be chosen to be substantially the same.
Regarding claim 9, Chen as modified in claim 1 teaches the glass manifold teaches a glass manifold (Choo: Fig 1 manifold 126, [0025]; Figs 14A, 14B, and 14C manifold assembly is made of glass, [0088]) comprises one or more glass manifold layers (Fig 14A cover layer 1431, Fig 14B intermediate layer 1433, and Fig 14C manifold 1426) and are CTE matched (Chen teaches the microchannel chip is made of silicon or glass [0012]; Choo teaches the manifold assembly is made of glass, [0088]; they would be CTE matched since they are made of substantially the same material) to the microchannel chip (Chen: Fig 12 substrate 12, [0018]).
Regarding claim 10, Chen as modified in claim 1 teaches the functional chips (Chen: Fig 12 package component 20A and 20B, [0019]) are rigidly bonded (metal to metal direct bonding, [0025]) to the microchannel cooler (Chen: Fig 12 substrate 12 and not shown pipe assembly, [0052]) with a low thermal resistance (the bond provides a good thermal path, [0023]; Examiner interprets this to mean there is low thermal resistance through the bond).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et. al. (US 20180366437 A1), hereinafter Chen, in view of Choo et. al. (US 20240096742 A1), hereinafter Choo, in further view of WaferPro (“Glass Wafer vs Silicon Wafer: An In-Depth Comparison” January 15, 2024, https://waferpro.com/glass-wafer-vs-silicon-wafer-an-in-depth-comparison/), hereinafter WaferPro, in further view of Chien et. al. (US 20230170279 A1), hereinafter Chien.
Regarding claim 2, Chen as modified in claim 1 teaches each semiconductor chip (Chen: Fig 12 package component 20A and 20B, [0019]) comprises a plurality of electrically conductive pillars (Chen: Fig 12 vias 44, [0032]) and is embedded in a chip-encapsulating molding compound-containing layer (Chen: Fig 12 gap-filling material 40, [0028]).
Chen fails to teach epoxy for the chip-encapsulating molding compound-containing layer.
However, Chien teaches a chip-encapsulating epoxy molding compound-containing layer (Fig 1 package component 136a, [0021]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen to incorporate the teachings of Chien by having the chip-encapsulating molding compound-containing layer being made of epoxy, as it was known in the art before the effective filing date of the claimed invention that epoxy could also be used to encapsulate chips ([0021]). MPEP 2144.07
Regarding claim 3, Chen as modified in claim 2 teaches the first RDL containing structure (Chen: Fig 12 RDLs, [0039]) comprises first metal wiring (Chen: Figs 12 and 14 metal line 56A1 and via 56A2, [0036]; associated with package component 20A) in electrical contact with a single semiconductor chip (Chen: Fig 12 package component 20A, [0019]) of the plurality of functional semiconductor chips (Chen: Fig 12 package component 20A and 20B, [0019]), and second metal wiring (Chen: Figs 12 and 14 metal line 56A1 and via 56A2, [0036]; that bridges components 20A and 20B) in electrical contact with a neighboring pair (Chen: Fig 12 package component 20A and 20B, [0019]) of functional semiconductor chips (Chen: Fig 12 package component 20A and 20B, [0019]) of the plurality of functional semiconductor chips (Chen: Fig 12 package component 20A and 20B, [0019]).
Examiner notes that it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that more than two packages can be used in the package 78 of Chen. Further, Chen teaches and shows metal wiring directly associated with a single component and metal wiring that bridges a pair of components (Fig 12).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et. al. (US 20180366437 A1), hereinafter Chen, in view of Choo et. al. (US 20240096742 A1), hereinafter Choo, in further view of WaferPro (“Glass Wafer vs Silicon Wafer: An In-Depth Comparison” January 15, 2024, https://waferpro.com/glass-wafer-vs-silicon-wafer-an-in-depth-comparison/), hereinafter WaferPro, in further view of Der Minassians et. al. (US 20190043567 A1), hereinafter Dermin.
Chen as modified in claim 1 fails to teach land grid array pads located above and in electrical contact with the first RDL containing structure (Fig 12 RDLs, [0039]).
However, Dermin teaches solder pads or land grid arrays can be used to interconnect packages ([0028]). In addition, Chen teaches conductive pads (Figs 11, 12, and 13 under-bump metallurgies UBMs 68, [0044]) to allow electrical connections to additional components.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen, Choo, and WaferPro to incorporate the teachings of Dermin by having land grid arrays above and in electrical contact with the first RDL containing structure, as it was known in the art before the effective filing date of the claimed invention that different interconnect conductors could be used interchangeably ([0028]). MPEP 2144.07
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et. al. (US 20180366437 A1), hereinafter Chen, in view of Choo et. al. (US 20240096742 A1), hereinafter Choo, in further view of WaferPro (“Glass Wafer vs Silicon Wafer: An In-Depth Comparison” January 15, 2024, https://waferpro.com/glass-wafer-vs-silicon-wafer-an-in-depth-comparison/), hereinafter WaferPro, in further view of Der Minassians et. al. (US 20190043567 A1), hereinafter Dermin, in further view of Hsu et. al. (US 20210074602 A1), hereinafter Hsu.
Regarding claim 5, Chen as modified in claim 4 fails to teach one or more additional RDL containing structures located between the land grid array pads and the first RDL containing structure, wherein the one or more additional RDL containing structures are in electrical contact with the first RDL containing structure and at least one of the land grid array pads.
However, Hsu teaches one or more additional RDL containing structures (Fig 1B interposer substrate 110, [0028]; Examiner notes the interposer substrate has the same features ([0029]) as the package substrate 102, also called a redistribution substrate by Hsu, [0018]) located between the land grid array pads (Fig 1B conductive elements 120 and 122, [0034] corresponds to Chen: Figs 11, 12, and 13 under-bump metallurgies UBMs 68, [0044]) and the first RDL containing structure (Fig 1B package substrate 102, [0018] corresponds to Chen: Fig 12 RDLs, [0039]), wherein the one or more additional RDL containing structures (Fig 1B interposer substrate 110, [0028]) are in electrical contact ([0017]) with the first RDL containing structure (Fig 1B package substrate 102, [0018] corresponds to Chen: Fig 12 RDLs, [0039]) and at least one of the land grid array pads (Fig 1B conductive elements 120 and 122, [0034] corresponds to Chen: Figs 11, 12, and 13 under-bump metallurgies UBMs 68, [0044]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen, Choo, WaferPro, and Dermin to incorporate the teachings of Hsu by having additional RDLs between land grid arrays and a first RDL. This would allow for additional design flexibility to increase yield ([0016]).
Regarding claim 6, Chen as modified in claim 5 teaches one or more additional RDL containing structures (Hsu: Fig 1B interposer substrate 110, [0028] are attached to the first RDL containing structure (Hsu: Fig 1B package substrate 102, [0018] corresponds to Chen: Fig 12 RDLs, [0039]) by solder balls (Hsu: Fig 1B conductive structures 116, [0028]), and the solder balls (Hsu: Fig 1B conductive structures 116, [0028]) are embedded in a non-conductive material (Hsu: Fig 1B underfill element 118, [0033]).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et. al. (US 20180366437 A1), hereinafter Chen, in view of Choo et. al. (US 20240096742 A1), hereinafter Choo, in further view of WaferPro (“Glass Wafer vs Silicon Wafer: An In-Depth Comparison” January 15, 2024, https://waferpro.com/glass-wafer-vs-silicon-wafer-an-in-depth-comparison/), hereinafter WaferPro, in further view of Chang et. al. (US 20240096849 A1), hereinafter Chang.
Regarding claim 7, Chen as modified in claim 1 fails to teach non-functional chips located face up on a second side of the microchannel chip, and spaced apart from each of the functional semiconductor chips of the plurality of functional semiconductor chips to largely fill the area not occupied by functional chips and are CTE matched to the microchannel chip.
However, Chang teaches non-functional chips (Fig 1 dummy dies 100B, [0039]) located face up on a second side (Fig 1 top side) of the microchannel chip (Fig 1 carrier 102, [0022] corresponds to Chen: Fig 12 substrate 12, [0018]), and spaced apart from (Fig 1) each of the functional semiconductor chips (Fig 1 semiconductor dies 100A, [0039] corresponds to Chen: Fig 12 package component 20A and 20B, [0019]) of the plurality of functional semiconductor chips (Fig 1 dies 100, [0039] corresponds to Chen: Fig 12 package component 20A and 20B, [0019]) to largely fill the area not occupied by functional chips and are CTE matched (Chang teaches the carrier is silicon [0022] and the semiconductor dies are made of silicon [0025]; thus they would be CTE matched since they are substantially made of the same material) to the microchannel chip (corresponds to Chen: Fig 12 substrate 12, [0018]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen, Choo, and WaferPro to incorporate the teachings of Chang by having non-functional chips. This would provide better warpage control ([0039]).
Regarding claim 8, Chen as modified in claim 7 teaches the non-functional chips (Chang: Fig 1 dummy dies 100B, [0039]) and the plurality of functional semiconductor chips (Chen: Fig 12 package component 20A and 20B, [0019]) are embedded in a chip-encapsulating epoxy molding compound-containing layer (Chang: Fig 2 encapsulation material 200m, [0041] corresponds to Chen: Fig 12 gap-filling material 40, [0028]; Chang teaches the encapsulation material can be epoxy or silica, [0041]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Patil et. al. (US 20210104507 A1) teaches bonding two different RDLs with solder and an underfill material to allow for increased flexibility in package configuration.
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN GAUTHIER can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
