Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 15-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/2/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/9/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 3 and 5-6 are objected to because of the following informalities: claim 3 contains the language “. . . a width at a vertical median level of the first plug portion is greater than each of the width of the second plug portion and the width of the third plug portion.” The examiner notes that the bolded word “width” is likely intended to be “widths.” Similar language appears in claim 5 and 6. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 20220344276 A1).
Regarding claim 10, Kim discloses, in FIG. 2, a semiconductor memory device (see paragraph 0028) comprising: a substrate 100, a “cell array region” (cell area) CAR and a “peripheral cell region” (peripheral area) adjacent to the cell area, a “lower insulating layer” (first interlayer insulating layer) 110 and an “first upper insulating layer” (first capping film) 150 disposed on the first interlayer insulating film, “bit lines” (one of which constitutes a first bit line structure) BL are disposed in the cell area of the substrate, a “peripheral transistor” (peripheral gate structure) PTR (the rightmost PTR in FIG. 2) is buried in the peripheral area of the substrate, and a peripheral contact plug (which is made up by “lower contact” 113, “first lower connection line” 131, a “second lower connection line” 133, “third lower connection line” 135, and “upper contact” 151, all disposed in the peripheral area) which extends through the first capping film and the first interlayer insulating film into the substrate, wherein a lower end of the peripheral contact plug is buried in the substrate, wherein a height of an upper surface of the first capping film pattern at a first position closest to a center of an upper surface of the peripheral gate structure is smaller than a height of the upper surface of the first capping film pattern at a second position closest to an upper end of the peripheral contact plug.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-5, 8-9, and 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20220344276 A1) in view of S. Kim (US 20220093610 A1).
Regarding claim 1, Kim discloses, in FIG. 2, a semiconductor memory device (see paragraph 0028) comprising: a substrate 100, a “cell array region” (cell area) CAR and a “peripheral cell region” (peripheral area) adjacent to the cell area, a “lower insulating layer” (first interlayer insulating layer) 110 and an “first upper insulating layer” (first capping film) 150 disposed on the first interlayer insulating film, “bit lines” (one of which constitutes a first bit line structure) BL are disposed in the cell area of the substrate, a “peripheral transistor” (peripheral gate structure) PTR (the rightmost PTR in FIG. 2) is buried in the peripheral area of the substrate, and a peripheral contact plug (which is made up by “lower contact” 113, “first lower connection line” 131, a “second lower connection line” 133, “third lower connection line” 135, and “upper contact” 151, all disposed in the peripheral area) which extends through the first capping film and the first interlayer insulating film, wherein the first capping film includes a first portion overlapping an upper surface of the peripheral gate structure and a second portion adjacent to a sidewall of the peripheral contact plug, an upper surface of the first portion being lower than an upper surface of the second portion, wherein the peripheral contact plug includes a first plug portion contacting the first interlayer insulating film, and a second plug portion contacting the first capping film.
Kim does not explicitly disclose that the first plug portion and the second plug portion are of equal width.
S. Kim teaches, in FIG. 18, a “TSV” disposed in “second peripheral region” p2 (peripheral contact plug) which has a first plug portion contacting an “interlayer dielectric layer” 133 and a second plug portion contacting a “contact hole hard mask” (capping layer) 133. The peripheral contact plug has a uniform width throughout the first and second plug portions (a width of the first plug portion is equal to a width of the second plug portion).
It would have been obvious to one having ordinary skill in the art to modify the device taught by Kim such that a width of the first plug portion is equal to a width of the second plug portion, as taught by S. Kim. One having ordinary skill in the art is motivated to do so to, for example, ensure that the peripheral contact plug does not taper to narrowly and is not able to be fully filled with material during manufacturing, ensure that the peripheral contact plug maintains sufficient width throughout its length to minimize resistance (thereby increasing efficiency), and/or to minimize the required width of the upper portion (as the upper portion of the contact hole needs to be wide enough to ensure that the peripheral contact plug can reach the first interlayer insulating film before it tapers down to a width of zero), minimizing parasitic capacitance between the upper plug and nearby components.
Regarding claim 2, Kim further teaches, in FIG. 2, that the peripheral contact plug further includes a third plug portion extending into the substrate and contacting the substrate.
Kim does not explicitly teach that the width of the second plug portion is equal to a width of the third plug portion.
As explained above, S. Kim teaches that the peripheral contact plug is of a uniform width throughout, FIG. 18 also shows that the peripheral contact plug has a third portion extending into the substrate 100.
It would have been obvious to one having ordinary skill in the art to modify the device taught by Kim such that the peripheral contact plug has a uniform width throughout (meaning that the third plug portion has the same width as the second plug portion), as taught by S. Kim. One having ordinary skill in the art is motivated to do so for the reasons stated above.
Regarding claim 4, Kim further teaches, in FIG. 2, a “second interlayer insulating layer” (second interlayer insulating film) disposed on the first capping film and a “upper interconnection line” (connection wiring) 171P disposed in the second interlayer insulating film and connected to the peripheral contact plug.
Regarding claim 5, Kim further teaches, in FIG. 2, that the width of the first connection wiring is greater than or equal to each of the width of the first plug portion and the width of the second plug portion.
Regarding claim 8, S. Kim further teaches that each of a sidewall of the first plug portion and a sidewall of the second plug portion extends in a vertical direction that is perpendicular to an upper surface of the substrate.
It would have been obvious to one of ordinary skill in the art to modify the device taught by S. Kim such that the peripheral plug has a uniform width throughout (and as a consequence the sidewalls of the first and second plug portions extend in a vertical direction that is perpendicular to an upper surface of the substrate), as taught by S. Kim. One having ordinary skill in the art is motivated to do so for the reasons explained above.
Regarding claim 9, as shown above, Kim teaches a plurality of bit lines in the cell area, paragraph 0025 states: “The bit lines BL may be spaced apart from each other in the second direction D2” (the second bit line structure is adjacent to the first bit line structure). FIG. 2 further shows “landing pads” (cell contact plug) disposed between bit line structures and connected to a “data storage pattern” DSS in which paragraph 0026 states “For example, the data storage structure DSS may include capacitors.”
Regarding claim 12, Kim further teaches, in FIG. 2, that the peripheral contact plug includes a first plug portion contacting the first interlayer insulating film, a second plug portion contacting the first capping film, and a third plug portion containing the substrate.
Kim does not explicitly teach that a width of the third plug portion is equal to a width of the second plug portion.
As explained above, S. Kim teaches a second and third plug portion in which the width is uniform throughout the peripheral contact plug’s length.
It would have been obvious to one having ordinary skill in the art to modify the device taught by Kim such that the peripheral contact plug has a uniform width throughout its length (as a consequence, the width of the third plug portion is equal to a width of the second plug portion). One having ordinary skill in the art is motivated to do so for the reasons explained above.
Regarding claim 13, Kim further teaches, in paragraph 0032: “An upper width of each of the first to third lower interconnection lines 131, 133 and 135 may be greater than a lower width thereof.” AS explained above, Kim does not teach a third plug portion.
As shown above, S. Kim teaches a third plug portion.
It would have been obvious to one having ordinary skill in the art to construct the semiconductor memory device taught by Kim such that the upper portions of the peripheral contact plug have a greater width than the lower portions of the peripheral contact plug (and therefore such that the width of the first plug portion is greater than each of the width of the second plug portion and a width of the third plug portion taught by S. Kim), as taught by Kim. One having ordinary skill in the art is motivated to do so in order to, for example, decrease the manufacturing cost of the device, as tapered (decreasing width) contact plugs can be formed with cheaper manufacturing methods, such as wet etching (as opposed to more expensive methods such as anisotropic photoetching, as an example). See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Regarding claim 14, Kim further teaches, in FIG. 2, a “second interlayer insulating layer” (second interlayer insulating film) disposed on the first capping film and a “upper interconnection line” (connection wiring) 171P disposed in the second interlayer insulating film and connected to the peripheral contact plug, wherein a width of the connection wiring is greater than each of the width of the first plug portion and the width of the second plug portion.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20220344276 A1) in view of S. Kim (US 20220093610 A1) in further view of Adusumilli (US 20170373006 A1)
Regarding claim 3, as explained above, Kim and S. Kim teach the limitations of claim 1, they do not teach a width at a vertical median level of the first plug portion that is greater than each of the widths of the second plug portion and the width of the third plug portion.
Adusumilli teaches, in FIG. 12, a “contact metallic region” (contact plug) which has a “biconvex shape” (paragraph 0071), in which a width at a vertical median level of the first plug portion is greater than each of the width of the second plug portion and the width of a lower plug portion.
It would have been obvious to one having ordinary skill in the art to modify the semiconductor memory device taught by Kim and S. Kim such that a width at a vertical median level of the first plug portion is greater than each of the widths of the second plug portion and the width of the bottom (third plug portion), as taught by Adusumilli. One having ordinary skill in the art is motivated to do so in order because “. . . each contact metallic region 64S [contact plug] having the biconvex shape may have a 20 percent to 40 percent increase in total volume as compared to a metallic region having perpendicular sidewall surfaces . . . Due to the increase in total volume of the contact metallic region 64S, a large reduction in wire resistance can be obtained” (Adusumilli, paragraph 0071).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20220344276 A1) in view of S. Kim (US 20220093610 A1) in further view of Cheon (US 20200402995 A1).
Regarding claim 6, as explained above, Kim and S. Kim teach the limitations of claim 4. They do not teach that a width of the connection wiring is smaller than the widths of the first and second plug portions.
Cheon teaches, in FIG. 1B, a semiconductor memory device with a “lower contact plug” 71 and an “upper contact plug” (connection wiring) 75, in which a width of the connection wiring is smaller than each of the widths of a first plug portion (going through “capping insulating layer” 47) and a second plug portion (going through “interlayer dielectric layer” 30).
It would have been obvious to one having ordinary skill in the art to further modify the semiconductor memory device taught by Kim and S. Kim such that a width of the connection wiring is smaller than each of the widths of the first and second plug portions, as taught by Cheon. One having ordinary skill in the art is motivated to do so in order to, for example, decrease the parasitic capacitance caused by the connection wiring.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20220344276 A1) in view of S. Kim (US 20220093610 A1)
Regarding claim 7, as shown above, Kim and S. Kim teach the limitations of claim 1. Kim further teaches, in FIG. 2, that the height of the upper surface of the first capping film increases from the upper surface of the first portion to an upper surface of the second portion. This “extension” are such that “a top surface of the second upper interlayer insulating layer 170 may not need to have a flat profile” (end of paragraph 0041).
It would have been obvious to one having ordinary skill in the art to modify the semiconductor device taught by Kim such that the first capping film has a curved upper surface. The examiner notes that the “extension” of the capping film 170 taught by Kim is cheaper to manufacture in embodiments in which there is a curvature in the extension portion (as sharp angles require specialized manufacturing techniques such as anisotropic etching or sacrificial layers). See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20220344276 A1) in view of J. Kim (US 20200035613 A1).
Regarding claim 11, as shown above, Kim teaches the limitations of claim 1. Kim further teaches, in FIG. 2, that the height of the upper surface of the first capping film increases from the upper surface of the first portion to an upper surface of the second portion.
Kim does not explicitly teach that the upper surface of the first capping film is curved.
J. Kim teaches, in FIG. 18, a “via contact” 240 which disposed in “IMD layer” (first interlayer insulating film) and a “upper wiring” 242 disposed in “upper insulating layer” (first capping film) 242, which make up a contact plug. A first portion of the capping film overlaps the “lower structures” 202 which “. . . may include a transistor” (paragraph 0084), which constitutes a gate structure, and a second portion which is adjacent to a sidewall of the contact plug. The capping film has a curved upper surface and has an increasing height from the first portion’s upper surface toward the upper surface of the second portion.
It would have been obvious to modify the semiconductor device taught by Kim such that the first capping film has a curved upper surface with an increasing height from the upper surface of the first portion of the first capping film toward the upper surface of the second portion of the first capping film, as taught by J. Kim. One having ordinary skill in the art is motivated to do so in order to, for example, decrease the manufacturing cost of the capping film taught by Kim, as creating an angular (non-curved) upper film is more costly to manufacture (as it requires precise deposition, sacrificial layers, and/or anisotropic etching to achieve).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Nagai (US 20050285173 A1) – Layers with an increasing height of an upper surface from buried gates to a portion which contacts sidewall of contact plugs.
Nagasaka (US 6300683 B1) – Contact plug which has a wider, tapered top and a narrower, untampered (straight) in lower portion.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL S MINNEY whose telephone number is (571)272-9688. The examiner can normally be reached Monday Friday, 8:30 a.m. 5 p.m. ET..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/G.S.M./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights