DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Invention I (Device), claims 1-6, in the reply filed on July 22, 2026 is acknowledged. Therefore, claims 1-6 are presented for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 6, Claim 6 recites the limitation "the source select line" in line 3. There is insufficient antecedent basis for this limitation in the claim, because “a source select line” was not previously introduced.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over by Kim (US 2023/0200068, Foreign priority: December 17, 2021 (KR), US filed on May 5, 2022) in view of Lue (US 2016/0260733).
Regarding claim 1, Kim discloses for A semiconductor memory device comprising:
a gate stack (gate stack bodies GST, Fig. 4) comprising interlayer insulating layers (insulating layers ILD, Fig. 4) and conductive pattern layers (conductive patterns CPn, Fig. 4), which are alternately stacked in a first direction (vertical direction, Fig. 4), the alternately stacked interlayer insulating layers (ILD, Fig. 4) and conductive pattern layers (CPn, Fig. 4) being supported by a substrate (substrate SUB, Fig. 4);
a channel structure (channel structure CH, Fig. 4) passing through the gate stack (GST, Fig. 4) in the first direction (vertical direction, Fig. 4), the channel structure (CH, Fig. 4) having a protruding end (upper end of channel structure CH, Fig. 4), which extends above a top surface of the gate stack (above top surface of topmost ILD of GST, Fig. 4);
a memory layer (memory layer ML, Fig. 4) surrounding the channel structure (CH, Fig. 4); and
a source layer (source layer SL, Fig. 4) formed on the gate stack (GST, Fig. 4),
wherein the channel structure (CH, Fig. 4) comprises:
a channel layer (channel layer 15, Fig. 4) surrounding the core insulating layer (core insulating layer 11, Fig. 4).
Kim differs from the claimed invention by not showing that a core insulating layer having a hollow central region and which comprises a VOID, wherein the VOID within the core insulating layer extends from a level below the lowest conductive pattern layer, upwardly in the first direction to a level, which is above the highest conductive pattern layer.
However, Lue discloses a vertical channel-type 3D semiconductor memory device including a gate stack which a plurality of intermediate planes of conductive strips (i.e., wordlines WLs, Figs. 11-18) and layers of insulating material 1121-1125 are alternately stacked (Figs. 11-18). Lue further discloses that a vertical channel structure 2000-2005 include a fill 1160 (insulating structure, [0137], Fig. 11) with a gap 1161 formed therein (air gap, [0092]), therefore, the fill 1160 corresponds to the claimed core insulating layer and the gap 1161 corresponds to the claimed VOID, and as shown in Figs. 11-18, the gap 1161 extends from the level below the lowest intermediate planes of conductive strip WL, upwardly in the vertical direction, which is above the highest intermediate planes of conductive strip WL.
Since both Kim and Lue teach a vertical channel semiconductor memory device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify Kim’s core insulating layer to include the hollow central void or airgap taught by Lue, and such modification would have used a known channel structure configuration to lower effective dielectric constant of the core insulating layer, reduce parasitic capacitance, and thereby improving the electrical performance the semiconductor memory device.
Regarding claim 2, Kim further discloses that the source layer comprises:
a first source layer (first source layer SL1 or 301, Fig. 4 or Fig. 8D) formed on an upper portion of the gate stack (upper portion of GST, Fig. 4) and around the protruding end of the channel structure (upper end of CH, Fig. 4); and a second source layer (third source layer SL3 or 305, Fig. 4 or Fig. 8D) formed on the first source layer (SL1, Fig. 4).
Regarding claim 3, Kim further discloses that a least a portion of the first source layer (301, Fig. 8D) contacts an upper portion of the channel layer (upper portion of the channel layer 141, Fig. 8D).
Regarding claim 4, Kim further discloses that the first source layer (301, Fig. 8D) is a doped polysilicon ([0099]).
Regarding claim 5, Kim further discloses that the second source layer (305, Fig. 8D) is a low-resistance metal, because “the third source layer 305 may be formed of a metal material having low resistance. For example, the third source layer 305 may be formed of tungsten W, thus reducing the resistance of the source line structure” (emphasis added, [0101]).
Regarding claim 6, Kim further discloses that the channel layer (141, Fig. 8D) includes a junction in a region adjacent to at least one conductive pattern layer (uppermost conductive pattern CPn, Fig. 4 or Fig. 8D) corresponding to the source select line, because the channel layer 141 by Kim includes a junction at the upper end of the channel layer in a region adjacent to the uppermost conductive pattern of the gate stack bodies GST (Fig. 8D), and Kim further discloses that “among the conductive patterns CP1 to CPn, an nth-conductive pattern CPn adjacent to a first source layer SL1, a second layer SL2, and a third source layer SL3 may be used as the source elect line SSL” ([0051]), therefore, the uppermost conductive pattern of the gate stack bodies by Kim may corresponds to the claimed source select line.
Conclusion
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/JAY C KIM/Primary Examiner, Art Unit 2815
/WOO K LEE/Examiner, Art Unit 2815
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