CTNF 18/659,539 CTNF 91724 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement 06-52 The information disclosure statement (IDS) submitted on 5/9/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification The abstract is consistent with the requirements set forth in the MPEP 608.01(b). 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. 06-11-01 AIA The following title is suggested: SEMICONDUCTOR PACKAGE COMPRISING CHIP WITH UPPER SURFACE HAVING GROOVES Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 6 recites the limitation "wherein the plurality of grooves comprise a first groove and a second groove, each having a depth that is smaller than a depth of the first groove" in lines 1-3. It is unclear how each (i.e. - each of the first groove and the second groove) can have a depth that is smaller than the depth of the first groove because the first groove can not have a depth smaller than the depth of itself. For examination purposes, the limitation is being interpreted as "wherein the plurality of grooves comprise a first groove and a second groove, each the second groove having a depth that is smaller than a depth of the first groove." Appropriate correction is required. Allowable Subject Matter Regarding claim 1, Kim et al., US PGPub. 2020/0402885 teaches a semiconductor package (700, fig. 14) [0093] comprising: a lower redistribution structure (110, fig. 14) [0026] including a lower redistribution layer (112-114, fig. 14) [0026]; a lower chip structure (120, fig. 14) [0040] disposed on the lower redistribution structure (110); an encapsulant (730, fig. 14) [0093] encapsulating at least a portion of the lower chip structure (120); an upper redistribution structure (810, fig. 14) [0094] disposed on the encapsulant and including an upper redistribution layer (similar to 112-114, fig. 14) [0094], [0026]; a plurality of posts (760, fig. 14) [0095] that pass through the encapsulant (730) and electrically connect the lower redistribution layer (110) and the upper redistribution layer (810); a plurality of external connection bumps (170, fig. 14) [0025] that are disposed below the lower redistribution structure (110) and electrically connect to the lower redistribution layer (110); and wherein the lower chip structure (120) has an upper surface having a plurality of grooves (121a, fig. 14) [0026] (Kim et al. fig. 14). But Kim fails to teach a cover layer including a first surface that contacts the lower chip structure and a second surface that is opposite to the first surface; the encapsulant (730) encapsulating at least a portion of the cover layer; and wherein the lower chip structure (120) includes: at least one stacked chip that contacts the first surface of the cover layer and has an upper surface having a plurality of grooves; a base chip disposed below the at least one stacked chip, the base chip including through-vias electrically connected to the at least one stacked chip and connection pads electrically connected to the lower redistribution layer; an adhesive layer disposed between the at least one stacked chip and the base chip and extending to the first surface of the cover layer along a side surface of the at least one stacked chip; and a mold surrounding an external side surface of the adhesive layer, wherein the cover layer includes a plurality of convex portions on the first surface that fill the plurality of grooves, and at least one concave portion on the second surface that is aligned on at least one convex portion among the plurality of convex portions. Regarding claim 15, Kim et al., US PGPub. 2020/0402885 teaches a semiconductor package (700, fig. 14) [0093] comprising: a redistribution structure (110, fig. 14) [0026] including a lower redistribution layer (112-114, fig. 14) [0026]; a chip structure (120, fig. 14) [0040] electrically connected to the redistribution layer (110) and having an upper surface having a plurality of grooves (121a, fig. 14) [0026]; an encapsulant (730, fig. 14) [0093] encapsulating at least a portion of the chip structure (120); and a plurality of external connection bumps (170, fig. 14) [0025] that are disposed below the redistribution structure (110) and electrically connect to the redistribution layer (110) (Kim et al., fig. 14). But Kim fails to teach a cover layer including a first surface that contacts the upper surface of the chip structure, and a second surface that is opposite to the first surface and has at least one concave portion that is aligned with at least one groove among the plurality of grooves; the encapsulant (730) at least a portion of the cover layer; and wherein the plurality of grooves (121a) include a first groove having a first curvature, the at least one concave portion includes a first concave portion that is aligned on the first groove, and the first concave portion has a second curvature that is smaller than the first curvature. Regarding claim 18, Kim et al., US PGPub. 2020/0402885 teaches a semiconductor package (700, fig. 14) [0093] comprising: a lower redistribution structure (110, fig. 14) [0026] including a lower redistribution layer (112-114, fig. 14) [0026]; a lower chip structure (120, fig. 14) [0040] including a lower surface on which connection terminals (160, fig. 14) [0025] that are electrically connected to the lower redistribution layer (110) are disposed, and an upper surface having a plurality of grooves (121a, fig. 14) [0026]; an encapsulant (730, fig. 14) [0093] encapsulating at least a portion of the lower chip structure (120); an upper redistribution structure (810, fig. 14) [0094] disposed on the encapsulant (730) and including an upper redistribution layer(similar to 112-114, fig. 14) [0094], [0026]; and a plurality of posts (760, fig. 14) [0095] that pass through the encapsulant (730) and electrically connect the lower redistribution layer (110) to the upper redistribution layer (810) (Kim et al., fig. 14). But Kim fails to teach a cover layer including a first surface that contacts the upper surface of the lower chip structure, and a second surface that is opposite to the first surface and has at least one concave portion that is aligned with at least one groove among the plurality of grooves; and the encapsulant (730) encapsulating at least a portion of the cover layer. Claims 1-5 and 7-20 are allowed. 13-03 AIA The following is an examiner’s statement of reasons for allowance: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a semiconductor package comprising a “lower chip structure includes: at least one stacked chip that contacts the first surface of the cover layer and has an upper surface having a plurality of grooves; a base chip disposed below the at least one stacked chip, the base chip including through-vias electrically connected to the at least one stacked chip and connection pads electrically connected to the lower redistribution layer; an adhesive layer disposed between the at least one stacked chip and the base chip and extending to the first surface of the cover layer along a side surface of the at least one stacked chip; and a mold surrounding an external side surface of the adhesive layer” in combination with the limitation wherein “the cover layer includes a plurality of convex portions on the first surface that fill the plurality of grooves, and at least one concave portion on the second surface that is aligned on at least one convex portion among the plurality of convex portions” as recited in claim 1; a semiconductor package comprising “a cover layer including a first surface that contacts the upper surface of the chip structure, and a second surface that is opposite to the first surface and has at least one concave portion that is aligned with at least one groove among the plurality of grooves” in combination with the limitation wherein “the plurality of grooves include a first groove having a first curvature, the at least one concave portion includes a first concave portion that is aligned on the first groove, and the first concave portion has a second curvature that is smaller than the first curvature” as recited in claim 15; and a semiconductor package comprising “a cover layer including a first surface that contacts the upper surface of the lower chip structure, and a second surface that is opposite to the first surface and has at least one concave portion that is aligned with at least one groove among the plurality of grooves” in combination with “an encapsulant encapsulating at least a portion of the lower chip structure and at least a portion of the cover layer” as recited in claim 18. Claims 2-5, 7-14, 16-17 and 19-20 are also allowed for further limiting and depending upon allowed claims 1, 15 and 18 . Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” 07-43-02 AIA Claim 6 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Bet-Shliemoun USW PGPub. 2015/0279761 teaches a semiconductor package (fig. 2) comprising a chip with grooves on the top surface and a thermal pad cover with grooves aligned with the grooves of the chip and Im et al., US PGPub. 2018/0269126 teaches a semiconductor package (fig. 1E) comprising a chip having grooves with a cover having grooves as well. But both cannot be reasonably combined with the closest prior art because they do not have any encapsulations that would cover them as claimed because the covers are for heat dissipation. Park US PGPub. 2022/0059473 teaches a semiconductor package (fig. 1) comprising a chip with grooves and a cover but the cover does not have grooves . Any inquiry concerning this communication or earlier communications from the examiner should be directed to NDUKA E OJEH whose telephone number is (571)270-0291. The examiner can normally be reached M-F; 9am - 5pm.. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NDUKA E OJEH/Primary Examiner, Art Unit 2892 Application/Control Number: 18/659,539 Page 2 Art Unit: 2892 Application/Control Number: 18/659,539 Page 3 Art Unit: 2892 Application/Control Number: 18/659,539 Page 4 Art Unit: 2892 Application/Control Number: 18/659,539 Page 5 Art Unit: 2892 Application/Control Number: 18/659,539 Page 6 Art Unit: 2892 Application/Control Number: 18/659,539 Page 7 Art Unit: 2892 Application/Control Number: 18/659,539 Page 8 Art Unit: 2892 Application/Control Number: 18/659,539 Page 9 Art Unit: 2892 Application/Control Number: 18/659,539 Page 10 Art Unit: 2892
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