Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 13, and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4, and 6-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. 2016/0155724 A1, hereinafter refer to Kim) in view of Ishikawa (U.S. 2014/0269108 A1, hereinafter refer to Ishikawa) and Huang et al. (U.S. 2013/0257564 A1, hereinafter refer to Huang).
Regarding Claim 1: Kim discloses an apparatus (see Kim, Fig.2 as shown below and ¶ [0005]), comprising
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a plurality of core chips (100/200) including a plurality of through-substrate vias (TSVs) (115/215) (see Kim, Fig.2 as shown above),
each of the core chips (100/200) including a plurality of channels (circuits) and a command circuit for each of the channels (note: integrated circuits 103 and 203 each includes a memory circuit, a logic circuit, or a combination thereof) (see Kim, Fig.2 as shown above),
wherein the plurality of core chips (100/200) are stacked with one another in a face-to-face (F- F) manner to define a common channel in first and second core chips (100/200), which face each other, of the plurality of core chips (100/200) (see Kim, Fig.2 as shown above and ¶ [0115]),
the first core chip (100) and the second core chip (200) include a first function circuit (103) and a second function circuit (203) coupled to the first function circuit (103) (see Kim, Fig.2 as shown above), respectively,
for corresponding channels (circuits) of the first and second core chips (100/200), the corresponding channels being the common channel (circuit) (see Kim, Fig.2 as shown above and Figs.3-4).
Kim is silent upon explicitly disclosing wherein a plurality of core chips including a plurality of spiral through-substrate vias (TSVs).
For support see Ishikawa, which teaches a plurality of core chips (21/22/23/24) including a plurality of spiral through-substrate vias (TSVs) (TSV_CS0 to TSV_CS3) (see Ishikawa, Fig.9 as shown below, ¶ [0005], and ¶ [0058]).
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Thus, it would have been within the scope of one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim and Ishikawa to enable the Kim’s through-substrate vias (TSVs) to be formed as spiral through-substrate vias (TSVs) as taught by Ishikawa in order to improve reliability of the ultimate product because one of ordinary skill in the art before effective filing date of the claimed invention would have been motivated to look to alternative suitable methods of performing the disclosed through-substrate vias (TSVs) and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
The combination of Kim and Ishikawa is silent upon explicitly disclosing wherein the first function circuit and the second function circuit include a logic circuit and a power supply circuit, respectively,
the logic circuit receives power from the power supply circuit,
the logic circuit controls the common channel of the first and second core chips,
the power supply circuit provides power to the first and second core chips, and
a signal processed by the logic circuit is provided to the power supply circuit and to another function circuit of the second core chip.
For support see Huang, which teaches wherein the first function circuit (logic) and the second function circuit (analog) include a logic circuit (logic) and a power supply circuit (analog), respectively (Huang, Fig.1 as shown below and ¶ [0013]- ¶ [0016]),
the logic circuit receives power from the power supply circuit (analog) (Huang, Fig.1 as shown below and ¶ [0013]- ¶ [0016]),
the logic circuit controls the common channel (circuits) of the first and second core chips (logic and analog circuits) (Huang, Fig.1 as shown below),
the power supply circuit (analog) provides power to the first and second core chips (logic and analog) (Huang, Fig.1 as shown below), and
a signal processed by the logic circuit is provided to the power supply circuit (analog) and to another function circuit of the second core chip (Huang, Fig.1 as shown below).
Note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim.
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teaching of Kim, Ishikawa, and Huang to enable the first function circuit (logic) and the second function circuit (analog) include a logic circuit (logic) and a power supply circuit (analog), respectively as taught by Huang in order to improve decoupling loads from high frequency noise, using less circuit area and having less current leakage.
Regarding Claim 2: Kim as modified teaches an apparatus as set forth in claim 1 as above. The combination of Kim, Ishikawa, and Huang further teaches wherein the logic circuit and the power supply circuit (analog) are coupled with each other by a bump (23) between the first and second core chips (Huang, Fig.1 as shown above), and
the power from the power supply circuit (analog) is supplied to the logic circuit through the bump (23) (Huang, Fig.1 as shown above).
Note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim.
Regarding Claim 4: Kim as modified teaches an apparatus as set forth in claim 1 as above. The combination of Kim, Ishikawa, and Huang further teaches wherein the logic circuit and the power supply circuit (analog) are coupled with each other by a bump (23) between the first and second core chips (Huang, Fig.1 as shown above), and
the power supply circuit (analog) receives the signal processed by the logic circuit through the bump (23) (Huang, Fig.1 as shown above).
Note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim.
Regarding Claim 6: Kim as modified teaches an apparatus as set forth in claim 1 as above. The combination of Kim, Ishikawa, and Huang is silent upon explicitly disclosing wherein the logic circuit and the power supply circuit are activated in response to a command signal provided by the spiral TSVs.
However, practicing the combination of Kim, Ishikawa, and Huang to modify the first function circuit and the second function circuit of the combination of Kim and Ishikawa to include a logic circuit (logic) and a power supply circuit (analog), respectively as taught by Huang necessarily results the claimed limitation of “the logic circuit and the power supply circuit are activated in response to a command signal provided by the spiral TSVs” as now specified in claim 8.
Regarding Claim 7: Kim as modified teaches an apparatus as set forth in claim 1 as above. The combination of Kim, Ishikawa, and Huang further teaches wherein the logic circuit includes a plurality of logic circuits (see Kim, Fig.2 as shown above and Fig.3),
the power supply circuit (analog) includes a plurality of power supply circuits (analog) (Huang, Fig.1 as shown above), and
the corresponding logic circuits and power supply circuits (analog) are coupled by a plurality of bumps (23) between the first and second core chips (Huang, Fig.1 as shown above).
Regarding Claim 8: Kim as modified teaches an apparatus as set forth in claim 1 as above. The combination of Kim, Ishikawa, and Huang further teaches wherein one or more non- spiral TSVs (see Ishikawa, Fig.9 as shown above).
Regarding Claim 9: Kim as modified teaches an apparatus as set forth in claim 1 as above. The combination of Kim, Ishikawa, and Huang further teaches wherein each of the core chips (100/200) includes a semiconductor substrate (111/211) and a plurality of wiring layers (113/213), and uppermost wiring layers of the first and second core chips (100/200) face each other (see Kim, Fig.2 as shown above).
Regarding Claim 10: Kim as modified teaches an apparatus as set forth in claim 1 as above. The combination of Kim, Ishikawa, and Huang further teaches wherein each of the core chips (100/200) includes one or more memory chips or memory dies (see Kim, Fig.2 as shown above).
Regarding Claim 11: Kim as modified teaches an apparatus as set forth in claim 1 as above. The combination of Kim, Ishikawa, and Huang further teaches wherein the core chips (100/200) are on an interface chip coupled to an interposer (300) (see Kim, Fig.2 as shown above and Fig.3).
Regarding Claim 12: Kim as modified teaches an apparatus as set forth in claim 1 as above. The combination of Kim, Ishikawa, and Huang further teaches wherein a plurality of bumps (BP) in alignment with the corresponding spiral TSVs (TSV_CS0 to TSV_CS3) and connecting the first and second core chips (21/22/23/24) (see Ishikawa, Fig.9 as shown above).
Regarding Claim 13: Kim discloses an apparatus (see Kim, Fig.2 as shown above and ¶ [0005]), comprising
a plurality of core chips (100/200) stacked with one another in a face-to-face (F-F) manner to provide shared functions between first and second core chips (100/200) (see Kim, Fig.2 as shown above and ¶ [0115]), each of the core chips (100/200) including:
a plurality of wiring layers (113/213) on a semiconductor substrate (111/211), uppermost wiring layers of the first and second core chips (100/200) facing each other (see Kim, Fig.2 as shown above);
a plurality of channels (circuits) and a command circuit for each of the channels (circuits), the channels (circuits) of the first and second core chips (100/200) corresponding with each other (see Kim, Fig.2 as shown above and Fig.3); and
a plurality of through-substrate vias (TSVs) (115/215) configured to provide command signals to the channels of the first and second core chips (115/215) (see Kim, Fig.2 as shown above),
Kim is silent upon explicitly disclosing wherein a plurality of spiral through-substrate vias (TSVs) configured to provide command signals to the channels of the first and second core chips in a spiral manner.
For support see Ishikawa, which teaches wherein a plurality of spiral through-substrate vias (TSVs) (TSV_CS0 to TSV_CS3) configured to provide command signals to the channels of the first and second core chips (21/22/23/24) in a spiral manner (see Ishikawa, Fig.9 as shown above, ¶ [0005], and ¶ [0058]).
Thus, it would have been within the scope of one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim and Ishikawa to enable the Kim’s through-substrate vias (TSVs) to be formed as spiral through-substrate vias (TSVs) as taught by Ishikawa in order to improve reliability of the ultimate product because one of ordinary skill in the art before effective filing date of the claimed invention would have been motivated to look to alternative suitable methods of performing the disclosed through-substrate vias (TSVs) and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
The combination of Kim and Ishikawa is silent upon explicitly disclosing wherein the first core chip and the second core chip include a logic circuit and a power supply circuit, respectively, for the corresponding channels as the shared functions,
the logic circuit receives power from the power supply circuit through a first bump between the first core chip and the second core chip, and
the power supply circuit receives a signal processed by the logic circuit through a second bump.
For support see Huang, which teaches wherein the first core chip (logic) and the second core chip (analog) include a logic circuit and a power supply circuit (analog), respectively, for the corresponding channels (devices) as the shared functions (Huang, Fig.1 as shown above and ¶ [0013]- ¶ [0016]),
the logic circuit receives power from the power supply circuit (analog) through a first bump (23) between the first core chip and the second core chip (Huang, Fig.1 as shown above), and
the power supply circuit (analog) receives a signal processed by the logic circuit through a second bump (23) (Huang, Fig.1 as shown above).
Note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim.
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teaching of Kim, Ishikawa, and Huang to enable the first core chip and the second core chip to include a logic circuit and a power supply circuit (analog) as taught by Huang in order to improve decoupling loads from high frequency noise, using less circuit area and having less current leakage.
Regarding Claim 14: Kim as modified teaches an apparatus as set forth in claim 13 as above. The combination of Kim, Ishikawa, and Huang further teaches wherein the logic circuit controls the channels of the first and second core chips (100/200) (note: integrated circuit 103 and 203 each includes a memory circuit, a logic circuit, or a combination thereof) (see Kim, Fig.2 as shown above).
Note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim.
Regarding Claim 15: Kim as modified teaches an apparatus as set forth in claim 13 as above. The combination of Kim, Ishikawa, and Huang is silent upon explicitly disclosing wherein the logic circuit and the power supply circuit are activated in response to the command signals provided by the spiral TSVs.
However, practicing the combination of Kim, Ishikawa, and Huang to modify the first core chip and the second core chip of the combination of Kim and Ishikawa to include a logic circuit (logic) and a power supply circuit (analog), respectively as taught by Huang necessarily results the claimed limitation of “the logic circuit and the power supply circuit are activated in response to the command signals provided by the spiral TSVs” as now specified in claim 15.
Regarding Claim 16: Kim as modified teaches an apparatus as set forth in claim 13 as above. The combination of Kim, Ishikawa, and Huang further teaches wherein each of the core chips (100/200) includes one or more memory chips or memory dies (see Kim, Fig.2 as shown above).
Regarding Claim 17: Kim as modified teaches an apparatus as set forth in claim 13 as above. The combination of Kim, Ishikawa, and Huang further teaches wherein a plurality of third bumps (117/217) in alignment with the TSVs (115/215) and connecting the first and second core chips (100/200) (see Kim, Fig.2 as shown above and Fig.3).
Claim(s) 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. 2016/0155724 A1, hereinafter refer to Kim) in view of Ishikawa (U.S. 2014/0269108 A1, hereinafter refer to Ishikawa) and Shikibu et al. (U.S. 2017/0033085 A1, hereinafter refer to Shikibu).
Regarding Claim 18: Kim discloses a memory device (see Kim, Fig.2 as shown above and ¶ [0005]), comprising
a plurality of memory dies (100/200) including a plurality of through-substrate vias (TSVs) (115/215) (see Kim, Fig.2 as shown above and Fig.3),
each of the memory dies (100/200) including a plurality of channels (circuits) and a command circuit for each of the channels (circuits) (see Kim, Fig.2 as shown above and Fig.3),
wherein the plurality of memory dies (100/200) are stacked with one another in a face-to-face (F-F) manner to define a common channel in first and second memory dies (100/200) (see Kim, Fig.2 as shown above and ¶ [0115]),
for corresponding channels (circuits) of the first and second memory dies, the corresponding channels being the common channel (see Kim, Fig.2 as shown above and Fig.3),
the logic circuit controls the common channel (circuits) of the first and second memory dies (100/200) (see Kim, Fig.2 as shown above and Fig.3).
Kim is silent upon explicitly disclosing wherein a plurality of memory dies including a plurality of spiral through-substrate vias.
For support see Ishikawa, which teaches wherein a plurality of memory dies (21/22/23/24) including a plurality of spiral through-substrate vias (TSV_CS0 to TSV_CS3) (see Ishikawa, Fig.9 as shown above, ¶ [0005], and ¶ [0058]).
Thus, it would have been within the scope of one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim and Ishikawa to enable the Kim’s through-substrate vias (TSVs) to be formed as spiral through-substrate vias (TSVs) as taught by Ishikawa in order to improve reliability of the ultimate product because one of ordinary skill in the art before effective filing date of the claimed invention would have been motivated to look to alternative suitable methods of performing the disclosed through-substrate vias (TSVs) and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
The combination of Kim and Ishikawa is silent upon explicitly disclosing wherein the first memory die and the second memory die include a logic circuit and a power supply circuit, respectively,
the logic circuit operates with power supplied from the power supply circuit through a bump between the first and second memory dies,
the power supply circuit further supplies power to another function circuit of the second memory die.
For support see Shikibu, which teaches wherein the first memory die (14) and the second memory die (13) include a logic circuit (LOG) and a power supply circuit (VDD/Rp), respectively (see Shikibu, Figs.1-2 as shown below and ¶ [0011]),
the logic circuit (LOG) operates with power supplied from the power supply circuit (VDD/Rp) through a bump between the first and second memory dies (14/13) (see Shikibu, Figs.1-2 as shown below and ¶ [0011]),
the power supply circuit (VDD/Rp) further supplies power to another function circuit of the second memory die (see Shikibu, Figs.1-2 as shown below and ¶ [0011]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim, Ishikawa, and Shikibu to enable the first memory die and the second memory die of the combination of Kim and Ishikawa to include a logic circuit and a power supply circuit as taught by Shikibu in order to suppress a parasitic capacitance of signal wires in micro-bump pads.
Regarding Claim 19: Kim as modified teaches a memory device as set forth in claim 18 as above. The combination of Kim, Ishikawa, and Shikibu further teaches wherein the power supply circuit (VDD/Rp) receives a signal processed by the logic circuit through the bump (see Shikibu, Figs.1-2 as shown above).
Note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim.
Regarding Claim 20: Kim as modified teaches a memory device as set forth in claim 18 as above. The combination of Kim, Ishikawa, and Shikibu further teaches wherein the bump includes a first bump (117/217) (see Kim, Fig.2 as shown above and Fig.3),
each of the memory dies (100/200) include a plurality of wiring layers (113/213) on a semiconductor substrate (111/211) (see Kim, Fig.2 as shown above and Fig.3),
uppermost wiring layers of the first and second memory dies (100/200) face each other (see Kim, Fig.2 as shown above and Fig.3),
the uppermost wiring layers of the first and second memory dies (100/200) are connected by the first bump (117/217) and a plurality of second bumps (117/217) (see Kim, Fig.2 as shown above and Fig.3),
the second bumps (BP) in alignment with the spiral TSVs (TSV_CS0 to TSV_CS3) (see Ishikawa, Fig.9 as shown above), and
the power from the power supply circuit is supplied to the logic circuit through the first bump (see Shikibu, Figs.1-2 as shown above), and
a command signal is supplied to the logic circuit and the power supply circuit through the spiral TSVs (TSV_CS0 to TSV_CS3) (see Ishikawa, Fig.9 as shown above).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
