CTNF 18/659,666 CTNF 89876 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (U.S. 2013/0257564 A1, hereinafter refer to Huang) in view of Kim et al. (U.S. 2016/0155724 A1, hereinafter refer to Kim) . Regarding Claim 1: Huang discloses an apparatus (see Huang, Fig.1 as shown below and ¶ [0013]), comprising PNG media_image1.png 325 546 media_image1.png Greyscale a plurality of core chips including a plurality of spiral through-substrate vias (TSVs) (see Huang, Fig.1 as shown above), wherein the plurality of core chips are stacked with one another (see Huang, Fig.1 as shown above), of the plurality of core chips, the first core chip and the second core chip include a first function circuit ( logic ) and a second function circuit ( analog ) coupled to the first function circuit, respectively (see Huang, Fig.1 as shown above), the first function circuit and the second function circuit provide a logic circuit and a power supply circuit ( analog ), respectively (see Huang, Fig.1 as shown above), and the logic circuit receives power from the power supply circuit ( analog ) (see Huang, Fig.1 as shown above). Huang is silent upon explicitly disclosing wherein the plurality of core chips are stacked with one another in a face-to-face manner to define a common channel in first and second core chips, which face each other. For support see Kim, which teaches wherein the plurality of core chips ( 100/200 ) are stacked with one another in a face-to-face manner to define a common channel in first and second core chips ( 100/200 ), which face each other (see Kim, Fig.2 as shown below and ¶ [0005]). PNG media_image2.png 484 796 media_image2.png Greyscale Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Huang and Kim to enable the Huang’s plurality of core chips to be stacked with one another in a face-to-face manner to define a common channel in first and second core chips, which face each other as taught by Kim in order to reduce the thickness of stacking structure. Regarding Claim 2: Huang as modified teaches an apparatus as set forth in claim 1 as above. The combination of Huang and Kim further teaches wherein the logic circuit and the power supply circuit ( analog ) are coupled with each other by a bump between the first ( logic ) and second core chips ( analog ) (see Huang, Fig.1 as shown above and ¶ [0040]), and the power from the power supply circuit ( analog ) is supplied to the logic circuit through the bump (see Huang, Fig.1 as shown above and ¶ [0040]). Regarding Claim 3: Huang as modified teaches an apparatus as set forth in claim 1 as above. The combination of Huang and Kim further teaches wherein the power supply circuit ( analog ) receives a signal processed by the logic circuit (see Huang, Fig.1 as shown above). Regarding Claim 4: Huang as modified teaches an apparatus as set forth in claim 1 as above. The combination of Huang and Kim further teaches wherein the logic circuit and the power supply circuit ( analog ) are coupled with each other by a bump between the first and second core chips (see Huang, Fig.1 as shown above and ¶ [0040]), and the power supply circuit ( analog ) receives a signal processed by the logic circuit through the bump (see Huang, Fig.1 as shown above and ¶ [0040]). Regarding Claim 5: Huang as modified teaches an apparatus as set forth in claim 1 as above. The combination of Huang and Kim further teaches wherein the logic circuit controls the common channel of the first ( logic ) and second core chips ( analog ) (see Huang, Fig.1 as shown above). Regarding Claim 6: Huang as modified teaches an apparatus as set forth in claim 1 as above. The combination of Huang and Kim further teaches wherein the logic circuit and the power supply circuit ( analog ) are activated in response to a command signal provided by the spiral TSVs (see Huang, Fig.1 as shown above). Regarding Claim 7: Huang as modified teaches an apparatus as set forth in claim 1 as above. The combination of Huang and Kim further teaches wherein the logic circuit includes a plurality of logic circuits (see Huang, Fig.1 as shown above), the power supply circuit ( analog ) includes a plurality of power supply circuits ( analog ), and the corresponding logic circuits and power supply circuits ( analog ) are coupled by a plurality of bumps between the first and second core chips (see Huang, Fig.1 as shown above and ¶ [0040]). Regarding Claim 8: Huang as modified teaches an apparatus as set forth in claim 1 as above. The combination of Huang and Kim further teaches wherein one or more non-spiral TSVs (see Huang, Fig.1 as shown above). Regarding Claim 9: Huang as modified teaches an apparatus as set forth in claim 1 as above. The combination of Huang and Kim further teaches wherein each of the core chips includes a semiconductor substrate and a plurality of wiring layers ( 213/113 ), and uppermost wiring layers of the first and second core chips face each other (see Kim, Fig.2 as shown above). Regarding Claim 10: Huang as modified teaches an apparatus as set forth in claim 1 as above. The combination of Huang and Kim further teaches wherein each of the core chips includes one or more memory chips or memory dies (see Kim, Fig.2 as shown above and see Huang, Fig.1 as shown above). Regarding Claim 11: Huang as modified teaches an apparatus as set forth in claim 1 as above. The combination of Huang and Kim further teaches wherein the core chips are on an interface chip coupled to an interposer (see Huang, Fig.1 as shown above). Regarding Claim 12: Huang as modified teaches an apparatus as set forth in claim 1 as above. The combination of Huang and Kim further teaches wherein a plurality of bumps in alignment with the corresponding spiral TSVs and connecting the first and second core chips (see Huang, Fig.1 as shown above and ¶ [0040]). Regarding Claim 13: Huang discloses an apparatus (see Huang, Fig.1 as shown above and ¶ [0013]), comprising a plurality of core chips stacked with one another other (see Huang, Fig.1 as shown above), each of the core chips including: a plurality of spiral through-substrate vias (TSVs) configured to provide command signals to the channels of the first and second core chips in a spiral manner (see Huang, Fig.1 as shown above), wherein the first core chip and the second core chip provide a logic circuit and a power supply circuit ( analog ), respectively, as the shared functions (see Huang, Fig.1 as shown above), the logic circuit receives power from the power supply circuit ( analog ) through a first bump between the first core chip and the second core chip (see Huang, Fig.1 as shown above), and the power supply circuit ( analog ) receives a signal processed by the logic circuit through a second bump (see Huang, Fig.1 as shown above). Huang is silent upon explicitly disclosing wherein a plurality of core chips stacked with one another other in a face-to-face manner to provide shared functions between first and second core chips, each of the core chips including: a plurality of wiring layers on a semiconductor substrate, uppermost wiring layers of the first and second core chips facing each other; a plurality of channels, the channels of the first and second core chips corresponding with each other. For support see Kim, which teaches wherein a plurality of core chips ( 100/200 ) stacked with one another other in a face-to-face manner to provide shared functions between first and second core chips ( 100/200 ) (see Kim, Fig.2 as shown above and ¶ [0005]), each of the core chips including: a plurality of wiring layers ( 113/213 ) on a semiconductor substrate, uppermost wiring layers of the first and second core chips ( 100/200 ) facing each other (see Kim, Fig.2 as shown above and ¶ [0005]); a plurality of channels, the channels of the first and second core chips ( 100/200 ) corresponding with each other (see Kim, Fig.2 as shown above and ¶ [0005]). Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Huang and Kim to enable the Huang’s plurality of core chips to be stacked with one another other in a face-to-face manner to provide shared functions between first and second core chips, each of the core chips including: a plurality of wiring layers on a semiconductor substrate, uppermost wiring layers of the first and second core chips facing each other, and the plurality of channels, the channels of the first and second core chips corresponding with each other as taught by Kim in order to reduce the thickness of stacking structure. Regarding Claim 14: Huang as modified teaches an apparatus as set forth in claim 13 as above. The combination of Huang and Kim further teaches wherein the logic circuit controls the channels of the first and second core chips (see Huang, Fig.1 as shown above). Regarding Claim 15: Huang as modified teaches an apparatus as set forth in claim 13 as above. The combination of Huang and Kim further teaches wherein the logic circuit and the power supply circuit ( analog ) are activated in response to the command signals provided by the spiral TSVs (see Huang, Fig.1 as shown above). Regarding Claim 16: Huang as modified teaches an apparatus as set forth in claim 13 as above. The combination of Huang and Kim further teaches wherein each of the core chips includes one or more memory chips or memory dies (see Huang, Fig.1 as shown above). Regarding Claim 17: Huang as modified teaches an apparatus as set forth in claim 13 as above. The combination of Huang and Kim further teaches wherein a plurality of third bumps in alignment with the TSVs and connecting the first and second core chips (see Huang, Fig.1 as shown above). Regarding Claim 18: Huang discloses a memory device (see Huang, Fig.1 as shown above and ¶ [0013]), comprising a plurality of memory dies including a plurality of spiral through-substrate vias (TSVs) (see Huang, Fig.1 as shown above), wherein the plurality of memory dies are stacked with one another (see Huang, Fig.1 as shown above), the first memory die and the second memory die provide a logic circuit and a power supply circuit ( analog ), respectively (see Huang, Fig.1 as shown above), and the logic circuit operates with power supplied from the power supply circuit ( analog ) through a bump between the first and second memory dies (see Huang, Fig.1 as shown above), and the logic circuit controls the common channel of the first and second memory dies (see Huang, Fig.1 as shown above). Huang is silent upon explicitly disclosing wherein the plurality of memory dies are stacked with one another other in a face-to-face manner to define a common channel in first and second memory dies. For support see Kim, which teaches wherein the plurality of memory dies ( 100/200 ) are stacked with one another other in a face-to-face manner to define a common channel in first and second memory dies (see Kim, Fig.2 as shown above and ¶ [0005]). Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Huang and Kim to enable the Huang’s plurality of memory dies to be stacked with one another other in a face-to-face manner to define a common channel in first and second memory dies as taught by Kim in order to reduce the thickness of stacking structure. Regarding Claim 19: Huang as modified teaches a memory device as set forth in claim 18 as above. The combination of Huang and Kim further teaches wherein the power supply circuit ( analog ) receives a signal processed by the logic circuit through the bump (see Huang, Fig.1 as shown above). Regarding Claim 20: Huang as modified teaches a memory device as set forth in claim 18 as above. The combination of Huang and Kim further teaches wherein the bump includes a first bump (see Huang, Fig.1 as shown above), each of the memory dies include a plurality of wiring layers ( 113/213 ) on a semiconductor substrate (see Kim, Fig.2 as shown above), uppermost wiring layers ( 113/213 ) of the first and second memory dies face each other, the upper most wiring layers of the first and second memory dies are connected by the first bump ( 117/217 ) and a plurality of second bumps ( 117/217 ), the second bumps in alignment with the spiral TSVs (see Kim, Fig.2 as shown above), and the power from the power supply circuit ( analog ) is supplied to the logic circuit through the first bump, and a command signal is supplied to the logic circuit and the power supply circuit through the spiral TSVs (see Huang, Fig.1 as shown above). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BITEW A DINKE/Primary Examiner, Art Unit 2812 Application/Control Number: 18/659,666 Page 2 Art Unit: 2812 Application/Control Number: 18/659,666 Page 3 Art Unit: 2812 Application/Control Number: 18/659,666 Page 4 Art Unit: 2812 Application/Control Number: 18/659,666 Page 5 Art Unit: 2812 Application/Control Number: 18/659,666 Page 6 Art Unit: 2812 Application/Control Number: 18/659,666 Page 7 Art Unit: 2812 Application/Control Number: 18/659,666 Page 8 Art Unit: 2812 Application/Control Number: 18/659,666 Page 9 Art Unit: 2812 Application/Control Number: 18/659,666 Page 10 Art Unit: 2812 Application/Control Number: 18/659,666 Page 11 Art Unit: 2812
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