Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks Pages.2-8, filed on 08/31/2026, with respect to the rejection(s) of claim(s) 1, 13, and 18 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kim and Ishikawa.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 13, and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “common channel" in line 4.
Claim 13 recites the limitation “channel" in line 6.
Claim 18 recites the limitation “common channel" in line 4.
The meaning of the term “channel” is indefinite because the term “channel” can be defined as “active region of the chips” or the “connection or the bonding region of the chips”
For purpose of compact prosecution, the term “channel” will be treated as if it were “connection or the bonding region of the chips.”
Claims 2-12, 14-17, and 19-20 are rejected as they were dependent on rejected claims 1, 13, and 18.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. 2016/0155724 A1, hereinafter refer to Kim) in view of Ishikawa (U.S. 2014/0269108 A1, hereinafter refer to Ishikawa).
Regarding Claim 1: Kim discloses an apparatus (see Kim, Fig.2 as shown below and ¶ [0005]), comprising
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a plurality of core chips (100/200) including a plurality of through-substrate vias (TSVs) (115/215) (see Kim, Fig.2 as shown above),
wherein the plurality of core chips (100/200) are stacked with one another in a face-to-face (F- F) manner to define a common channel in first and second core chips (100/200), which face each other, of the plurality of core chips (100/200) (see Kim, Fig.2 as shown above and ¶ [0115]),
the first core chip (100) and the second core chip (200) include a first function circuit (103) and a second function circuit (203) coupled to the first function circuit (103) (see Kim, Fig.2 as shown above), respectively,
the first function circuit (100) and the second function circuit (200) provide a logic circuit and a power supply circuit (note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim) (note: integrated circuit 103 and 203 each includes a memory circuit, a logic circuit, or a combination thereof) (note: Kim, Fig.3 teaches chip 200 function as a power supply circuit for chip 100 because chip 200 electrically connected to external power source through third semiconductor chip 300) (see Kim, Fig.2 as shown above), respectively, and
the logic circuit receives power from the power supply circuit (note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim) (note: integrated circuit 103 and 203 each includes a memory circuit, a logic circuit, or a combination thereof) (see Kim, Fig.2 as shown above).
Kim is silent upon explicitly disclosing wherein a plurality of core chips including a plurality of spiral through-substrate vias (TSVs).
For support see Ishikawa, which teaches a plurality of core chips (21/22/23/24) including a plurality of spiral through-substrate vias (TSVs) (TSV_CS0 to TSV_CS3) (see Ishikawa, Fig.9 as shown below, ¶ [0005], and ¶ [0058]).
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Thus, it would have been within the scope of one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim and Ishikawa to enable the Kim’s through-substrate vias (TSVs) to be formed as spiral through-substrate vias (TSVs) as taught by Ishikawa in order to improve reliability of the ultimate product because one of ordinary skill in the art before effective filing date of the claimed invention would have been motivated to look to alternative suitable methods of performing the disclosed through-substrate vias (TSVs) and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Regarding Claim 2: Kim as modified teaches an apparatus as set forth in claim 1 as above. The combination of Kim and Ishikawa further teaches wherein the logic circuit and the power supply circuit are coupled with each other by a bump (117/217) between the first and second core chips (note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim ) (see Kim, Fig.2 as shown above), and
the power from the power supply circuit is supplied to the logic circuit through the bump (117/217) (note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim ) (see Kim, Fig.2 as shown above).
Regarding Claim 3: Kim as modified teaches an apparatus as set forth in claim 1 as above. The combination of Kim and Ishikawa further teaches wherein the power supply circuit receives a signal processed by the logic circuit (note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim ) (see Kim, Fig.2 as shown above).
Regarding Claim 4: Kim as modified teaches an apparatus as set forth in claim 1 as above. The combination of Kim and Ishikawa further teaches wherein the logic circuit and the power supply circuit are coupled with each other by a bump (117/217) between the first and second core chips (100/200) (note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim ) (see Kim, Fig.2 as shown above), and
the power supply circuit receives a signal processed by the logic circuit through the bump (117/217) (note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim) (see Kim, Fig.2 as shown above).
Regarding Claim 5: Kim as modified teaches an apparatus as set forth in claim 1 as above. The combination of Kim and Ishikawa further teaches wherein the logic circuit controls the common channel of the first and second core chips (100/200) (note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim) (see Kim, Fig.2 as shown above).
Regarding Claim 6: Kim as modified teaches an apparatus as set forth in claim 1 as above. The combination of Kim and Ishikawa further teaches wherein the logic circuit and the power supply circuit are activated in response to a command signal provided by the spiral TSVs (see Ishikawa, Fig.9 as shown above).
Regarding Claim 7: Kim as modified teaches an apparatus as set forth in claim 1 as above. The combination of Kim and Ishikawa further teaches wherein the logic circuit includes a plurality of logic circuits (note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim) (see Kim, Fig.2 as shown above and Fig.3),
the power supply circuit includes a plurality of power supply circuits (note: integrated circuit 103 and 203 each includes a memory circuit, a logic circuit, or a combination thereof) (note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim) (see Kim, Fig.2 as shown above and Fig.3), and
the corresponding logic circuits and power supply circuits are coupled by a plurality of bumps (117/217) between the first and second core chips (note: integrated circuit 103 and 203 each includes a memory circuit, a logic circuit, or a combination thereof) (100/200) (note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim) (see Kim, Fig.2 as shown above and Fig.3).
Regarding Claim 8: Kim as modified teaches an apparatus as set forth in claim 1 as above. The combination of Kim and Ishikawa further teaches wherein one or more non- spiral TSVs (see Ishikawa, Fig.9 as shown above).
Regarding Claim 9: Kim as modified teaches an apparatus as set forth in claim 1 as above. The combination of Kim and Ishikawa further teaches wherein each of the core chips (100/200) includes a semiconductor substrate (111/211) and a plurality of wiring layers (113/213), and uppermost wiring layers of the first and second core chips (100/200) face each other (see Kim, Fig.2 as shown above).
Regarding Claim 10: Kim as modified teaches an apparatus as set forth in claim 1 as above. The combination of Kim and Ishikawa further teaches wherein each of the core chips (100/200) includes one or more memory chips or memory dies (see Kim, Fig.2 as shown above).
Regarding Claim 11: Kim as modified teaches an apparatus as set forth in claim 1 as above. The combination of Kim and Ishikawa further teaches wherein the core chips (100/200) are on an interface chip coupled to an interposer (300) (see Kim, Fig.2 as shown above and Fig.3).
Regarding Claim 12: Kim as modified teaches an apparatus as set forth in claim 1 as above. The combination of Kim and Ishikawa further teaches wherein a plurality of bumps (BP) in alignment with the corresponding spiral TSVs (TSV_CS0 to TSV_CS3) and connecting the first and second core chips (21/22/23/24) (see Ishikawa, Fig.9 as shown above).
Regarding Claim 13: Kim discloses an apparatus (see Kim, Fig.2 as shown above and ¶ [0005]), comprising
a plurality of core chips (100/200) stacked with one another other in a face-to-face (F-F) manner to provide shared functions between first and second core chips (100/200) (see Kim, Fig.2 as shown above and ¶ [0115]), each of the core chips (100/200) including:
a plurality of wiring layers (113/213) on a semiconductor substrate (111/211), uppermost wiring layers of the first and second core chips (100/200) facing each other (see Kim, Fig.2 as shown above);
a plurality of channels, the channels of the first and second core chips (100/200) corresponding with each other (see Kim, Fig.2 as shown above and Fig.3); and
a plurality of through-substrate vias (TSVs) (115/215) configured to provide command signals to the channels of the first and second core chips (115/215) (see Kim, Fig.2 as shown above),
wherein the first core chip (100) and the second core chip (200) provide a logic circuit and a power supply circuit, respectively, as the shared functions (note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim) (note: integrated circuit 103 and 203 each includes a memory circuit, a logic circuit, or a combination thereof) (see Kim, Fig.2 as shown above),
the logic circuit receives power from the power supply circuit through a first bump (117/217) between the first core chip and the second core chip (100/200) (note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim) (note: integrated circuit 103 and 203 each includes a memory circuit, a logic circuit, or a combination thereof) (note: Kim, Fig.3 teaches chip 200 function as a power supply circuit and a signal output circuit for or/and from chip 100 because chip 200 electrically connected to external power source and external device through third semiconductor chip 300) (see Kim, Fig.2 as shown above), and
the power supply circuit receives a signal processed by the logic circuit through a second bump (117/217) (note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim) (note: integrated circuit 103 and 203 each includes a memory circuit, a logic circuit, or a combination thereof) (note: Kim, Fig.3 teaches chip 200 function as a power supply circuit and a signal output circuit for or/and from chip 100 because chip 200 electrically connected to external power source and external device through third semiconductor chip 300) (see Kim, Fig.2 as shown above and Fig.3).
Kim is silent upon explicitly disclosing wherein a plurality of spiral through-substrate vias (TSVs) configured to provide command signals to the channels of the first and second core chips in a spiral manner.
For support see Ishikawa, which teaches wherein a plurality of spiral through-substrate vias (TSVs) (TSV_CS0 to TSV_CS3) configured to provide command signals to the channels of the first and second core chips (21/22/23/24) in a spiral manner (see Ishikawa, Fig.9 as shown above, ¶ [0005], and ¶ [0058]).
Thus, it would have been within the scope of one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim and Ishikawa to enable the Kim’s through-substrate vias (TSVs) to be formed as spiral through-substrate vias (TSVs) as taught by Ishikawa in order to improve reliability of the ultimate product because one of ordinary skill in the art before effective filing date of the claimed invention would have been motivated to look to alternative suitable methods of performing the disclosed through-substrate vias (TSVs) and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Regarding Claim 14: Kim as modified teaches an apparatus as set forth in claim 13 as above. The combination of Kim and Ishikawa further teaches wherein the logic circuit controls the channels of the first and second core chips (100/200) (note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim) (note: integrated circuit 103 and 203 each includes a memory circuit, a logic circuit, or a combination thereof) (see Kim, Fig.2 as shown above).
Regarding Claim 15: Kim as modified teaches an apparatus as set forth in claim 13 as above. The combination of Kim and Ishikawa further teaches wherein the logic circuit and the power supply circuit are activated in response to the command signals provided by the spiral TSVs (see Ishikawa, Fig.9 as shown above).
Regarding Claim 16: Kim as modified teaches an apparatus as set forth in claim 13 as above. The combination of Kim and Ishikawa further teaches wherein each of the core chips (100/200) includes one or more memory chips or memory dies (see Kim, Fig.2 as shown above).
Regarding Claim 17: Kim as modified teaches an apparatus as set forth in claim 13 as above. The combination of Kim and Ishikawa further teaches wherein a plurality of third bumps (117/217) in alignment with the TSVs (115/215) and connecting the first and second core chips (100/200) (see Kim, Fig.2 as shown above and Fig.3).
Regarding Claim 18: Kim discloses a memory device (see Kim, Fig.2 as shown above and ¶ [0005]), comprising
a plurality of memory dies (100/200) including a plurality of through-substrate vias (TSVs) (115/215) (see Kim, Fig.2 as shown above and Fig.3),
wherein the plurality of memory dies (100/200) are stacked with one another other in a face-to-face (F-F) manner to define a common channel in first and second memory dies (100/200) (see Kim, Fig.2 as shown above and ¶ [0115]),
the first memory die (100) and the second memory die (200) provide a logic circuit and a power supply circuit, respectively (note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim) (note: integrated circuit 103 and 203 each includes a memory circuit, a logic circuit, or a combination thereof) (note: Kim, Fig.3 teaches chip 200 function as a power supply circuit and a signal output circuit for or/and from chip 100 because chip 200 electrically connected to external power source and external device through third semiconductor chip 300) (see Kim, Fig.2 as shown above and Fig.3), and
the logic circuit operates with power supplied from the power supply circuit through a bump (117/217) between the first and second memory dies (100/200) (note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim) (note: integrated circuit 103 and 203 each includes a memory circuit, a logic circuit, or a combination thereof) (note: Kim, Fig.3 teaches chip 200 function as a power supply circuit and a signal output circuit for or/and from chip 100 because chip 200 electrically connected to external power source and external device through third semiconductor chip 300) (see Kim, Fig.2 as shown above and Fig.3), and
the logic circuit controls the common channel of the first and second memory dies (100/200) (note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim) (note: integrated circuit 103 and 203 each includes a memory circuit, a logic circuit, or a combination thereof) (see Kim, Fig.2 as shown above and Fig.3).
Kim is silent upon explicitly disclosing wherein a plurality of memory dies including a plurality of spiral through-substrate vias.
For support see Ishikawa, which teaches wherein a plurality of memory dies (21/22/23/24) including a plurality of spiral through-substrate vias (TSV_CS0 to TSV_CS3) (see Ishikawa, Fig.9 as shown above, ¶ [0005], and ¶ [0058]).
Thus, it would have been within the scope of one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim and Ishikawa to enable the Kim’s through-substrate vias (TSVs) to be formed as spiral through-substrate vias (TSVs) as taught by Ishikawa in order to improve reliability of the ultimate product because one of ordinary skill in the art before effective filing date of the claimed invention would have been motivated to look to alternative suitable methods of performing the disclosed through-substrate vias (TSVs) and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Regarding Claim 19: Kim as modified teaches a memory device as set forth in claim 18 as above. The combination of Kim and Ishikawa further teaches wherein the power supply circuit receives a signal processed by the logic circuit through the bump (117/217) (note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” since the prior art apparatus teaches all the structural limitations of the claim) (note: integrated circuit 103 and 203 each includes a memory circuit, a logic circuit, or a combination thereof) (note: Kim, Fig.3 teaches chip 200 function as a power supply circuit and a signal output circuit for or/and from chip 100 because chip 200 electrically connected to external power source and external device through third semiconductor chip 300) (see Kim, Fig.2 as shown above and Fig.3).
Regarding Claim 20: Kim as modified teaches a memory device as set forth in claim 18 as above. The combination of Kim and Ishikawa further teaches wherein the bump includes a first bump (117/217) (see Kim, Fig.2 as shown above and Fig.3),
each of the memory dies (100/200) include a plurality of wiring layers (113/213) on a semiconductor substrate (111/211) (see Kim, Fig.2 as shown above and Fig.3),
uppermost wiring layers of the first and second memory dies (100/200) face each other (see Kim, Fig.2 as shown above and Fig.3),
the uppermost wiring layers of the first and second memory dies (100/200) are connected by the first bump (117/217) and a plurality of second bumps (117/217) (see Kim, Fig.2 as shown above and Fig.3),
the second bumps (BP) in alignment with the spiral TSVs (TSV_CS0 to TSV_CS3) (see Ishikawa, Fig.9 as shown above), and
the power from the power supply circuit is supplied to the logic circuit through the first bump (117/217) (note: Kim, Fig.3 teaches chip 200 function as a power supply circuit and a signal output circuit for or/and from chip 100 because chip 200 electrically connected to external power source and external device through third semiconductor chip 300) (see Kim, Fig.2 as shown above and Fig.3), and
a command signal is supplied to the logic circuit and the power supply circuit through the spiral TSVs (TSV_CS0 to TSV_CS3) (see Ishikawa, Fig.9 as shown above).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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