CTNF 18/659,703 CTNF 91783 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement 06-52 The information disclosure statement (IDS) submitted on 5/9/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-3, 5-6, and 8-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. US 2017/0103951 in view Hu et al. US 2015/0049441 and Chiang et al. US 2020/0269556 . Re claim 1 , Lee teaches a semiconductor package (fig9 and 10), comprising: a lower redistribution structure (140, fig9, [108]) including a lower redistribution layer (142a/b, fig9, [108]); an interconnection structure (110, fig9, [96]) disposed on the lower redistribution structure (140, fig9, [108]), the interconnection structure (110, fig9, [96]) having internal side surfaces defining a through-portion (110H, fig9, [95]), external side surfaces (surface of 110 facing away from 121, fig9 and 10, [96, 101]) opposite to the internal side surfaces (surface of 110 facing 121, fig9 and 10, [96, 101]). Lee does not explicitly show corner surfaces defining recess portions, wherein the corner surfaces are between adjacent external side surfaces. Hu teaches corner surfaces defining recess portions (105a, 100a, 110a and 115a, fig3, [34]), wherein the corner surfaces are between adjacent external side surfaces (side surface of 70 facing away from 75 and overlap with 75, fig3). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lee and Hu to recess the corner of 110 in Lee fig9. The motivation to do so is to reduce warpage (Hu, [9]). Lee in view of Hu teaches the interconnection structure (Lee, 110, fig9, [96]) including a fiber layer (Lee, 111a/b as pre impregnated composite fiber (prepreg), fig9, [97]) having first fiber ends adjacent to at least a portion of the corner surfaces (fiber ends of prepreg located at recessed corners of Lee 110 as shown by Hu fig3). Lee does not explicitly show the detail of prepreg with an insulating resin layer in which the fiber layer is embedded. Chiang teaches prepreg with fiber ends (10 and 20, fig1, [13]) adjacent to exposed outer surfaces and an insulating resin layer (30, fig1, [12]) in which the fiber layer is embedded. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lee in view of Hu and Chiang to form the prepreg with the process of Chiang. The motivation to do so is to achieve both strength and weight reduction and improve yield and production throughput (Chiang, [2, 30-34]). Lee modified above teaches an interconnection layer (Lee, 112c, fig9, [96]) disposed on at least one surface of the insulating resin layer (Lee, 111b, fig9, [97]) and electrically connected to the lower redistribution layer (Lee, 140, fig9, [108]); a semiconductor chip (Lee, 120, fig9, [90]) disposed in the through-portion (Lee, 110H, fig9, [90]) of the interconnection structure and including connection pads (Lee, 122, fig9, [90]) electrically connected to the lower redistribution layer (Lee, 140, fig9, [108]); an encapsulant (Lee, 130, fig9, [135]) disposed in the through-portion (Lee, 110H, fig9, [90]); Embodiment of Lee in fig 9-10 does not explicitly show an encapsulant disposed in the recess portions of the interconnection structure; Embodiment of Lee in fig17 and 18 teaches an encapsulant (130, fig17, [135]) disposed in the through-portion (110H, fig17, [90]) and the recess portions (130 cover region between 110A-E in the corner region, fig18) of the interconnection structure; It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to cover all exposed surfaces of the interconnection structure 110 with recessed corners and form 110A-E as 70 of Hu with recessed corners. The motivation to do so is to protect the interconnect from the environment (Lee, [86, 81]) and reduce warp due to mismatch in coefficient of thermal expansion of Lee 110 and 130 (Hu, [8]). Lee modified above teaches an upper redistribution structure (Lee, 180, 182, 184, fig19, [138]) disposed on the encapsulant (Lee, 130, fig19, [138]) and including an upper redistribution layer (Lee, 182 and 184, fig19, [138]) electrically connected to the interconnection layer (Lee, 112c, fig9, [96]); and connection bumps (Lee, 170, fig19, [90]) disposed below the lower redistribution structure (Lee, 140, fig9, [108]) and electrically connected to the lower redistribution layer (Lee, 142a/b, fig9, [108]). Re claim 2 , Lee modified above teaches the semiconductor package of claim 1, wherein the interconnection structure (Lee, 110, fig9, [96]; ) has a pattern region (Lee, center part of 110 located inside the recessed corners, fig10; ) around the through-portion (Lee, 110H, fig9, [90]) in which the interconnection layer (Lee, 112c, fig9, [96]) is disposed and a margin region around the pattern region (Hu, region around recess 105a, 100a, 110a and 115a, fig3, [34]), and each of the recess portions has a first horizontal width in a first direction and a second horizontal width in a second direction equal to or greater than a width of the margin region on a horizontal plane (Hu, fig2 and 3). Re claim 3 , Lee modified above teaches the semiconductor package of claim 2, wherein the recess portions are disposed in the margin region (Hu, region around recess 105a, 100a, 110a and 115a, fig3, [34]). Re claim 5 , Lee modified above teaches the semiconductor package of claim 2, wherein the first horizontal width and the second horizontal width of the recess portions are the same as one another (Hu, width and length of 105a, 100a, 110a and 115a are about the same, fig3, [34]). Re claim 6, Lee modified above teaches the semiconductor package of claim 1, wherein the encapsulant (Lee, 130, fig17, [135]) in a first recess portion of the recess portions has external surfaces extending from two external side surfaces of the interconnection structure (Lee, 110A-E, fig18, [96]), and wherein the first fiber ends of the fiber layer are spaced apart from the external surfaces (Lee, fiber of prepreg 111a/b spaced apart from outer surface of 130, fig17). Re claim 8 , Lee modified above teaches the semiconductor package of claim 1, wherein the fiber layer has second fiber ends (Chiang, fiber end of 10 and 20 located at exposed surface of resin 30, fig1, [13]) adjacent to at least a portion of the external side surfaces (Lee, surface of 110 facing away from 121, fig17, [96, 101]). Re claim 9 , Lee modified above teaches the semiconductor package of claim 1, wherein the fiber layer is woven with first fibers arranged in a first direction and second fibers arranged in a second direction intersecting the first direction (Chiang, 10 or 20 formed with fiber cross each other, fig1, [13]). Re claim 10 , Lee modified above teaches the semiconductor package of claim 9, wherein the first fiber ends are provided by at least a portion of the first fibers and the second fibers (Chiang, fiber end of 10 and 20 located at exposed surface of resin 30, fig1, [13]). Re claim 11 , Lee modified above teaches the semiconductor package of claim 1, wherein the corner surfaces are curved surfaces connecting ends of adjacent external side surfaces (Hu, fig10 or 12). Re claim 12 , Lee modified above teaches the semiconductor package of claim 1, wherein the corner surfaces are planes connecting ends of adjacent external side surfaces (Hu, fig6). Re claim 13 , Lee modified above teaches the semiconductor package of claim 1, wherein the corner surfaces are bent surfaces connecting ends of adjacent external side (Hu, 105c, 110c, 100c and 115c, fig6 ). Re claim 14 , Lee teaches a semiconductor package (fig9 and 10), comprising: a lower redistribution structure (140, fig9, [108]) including a lower redistribution layer (142a/b, fig9, [108]); a semiconductor chip (120, fig9, [90]) disposed on the lower redistribution structure and including connection pads (122, fig9, [90]) electrically connected to the lower redistribution layer; an interconnection structure (110, fig9, [96]) surrounding the semiconductor chip, Lee does not explicitly show the interconnection structure having external side surfaces and corner surfaces between adjacent external side surfaces. Hu teaches the interconnection structure having external side surfaces (side surface of 70 facing away from 75 and overlap with 75, fig3) and corner surfaces (two side surface of each 105a, 100a, 110a and 115a, fig3, [34]) between adjacent external side surfaces. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lee and Hu to recess the corner of 110 in Lee fig9. The motivation to do so is to reduce warpage (Hu, [9]). Lee in view of Hu teaches the interconnection structure (Lee, 110, fig9, [96]) including an insulating resin layer with an insulating resin impregnated in a fiber layer (Lee, 111a/b as pre impregnated composite fiber (prepreg), fig9, [97]), interconnection layers (Lee, 112c and 112a, fig9, [96]) disposed on two surfaces of the insulating resin layer, and an interconnection via (Lee, 113b, 112b and 113a, fig11A) penetrating the insulating resin layer and electrically connecting the interconnection layers to each other; an encapsulant (Lee, 130, fig17, [135]) covering at least a portion of each of the semiconductor chip and the interconnection structure; and an upper redistribution structure (Lee, 180, 182, 183, 184, fig19, [138]) including an insulating layer (Lee, 180, fig19, [138]) disposed on the encapsulant, an upper redistribution layer (Lee, 182, fig19, [138]) on the insulating layer, and an upper redistribution via (Lee, 183, fig19, [138]) penetrating the insulating layer (Lee, 180, fig19, [138]) and electrically connecting the upper redistribution layer (Lee, 182, fig19, [138]) to the interconnection layers (Lee, 112c and 112a, fig19, [96]), Lee does not explicitly show wherein the fiber layer has fiber ends with at least a portion cut-out by the corner surfaces. Chiang teaches prepreg with fiber ends (10 and 20, fig1, [13]) adjacent to exposed outer surfaces and an insulating resin layer (30, fig1, [12]) in which the fiber layer is embedded. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lee in view of Hu and Chiang to form the prepreg with the process of Chiang. The motivation to do so is to achieve both strength and weight reduction and improve yield and production throughput (Chiang, [2, 30-34]). Re claim 15 , Lee modified above teaches the semiconductor package of claim 14, wherein the encapsulant includes a first portion covering a side surface and an upper surface of the semiconductor chip (Lee, 130 around 120, fig17, [135]), Embodiment of Lee fig 9-10 does not explicitly show a second portion extending from the first portion and covering an upper surface and the corner surfaces of the interconnection structure. Lee fig17 and 18 teaches a second portion (Lee, corner part of 130 formed around 110A-E, fig18) extending from the first portion (Lee, 130 around 121, fig18) and covering an upper surface and the corner surfaces of the interconnection structure. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to cover all exposed surfaces of the interconnection structure 110 with recessed corners and form 110A-E as 70 of Hu with recessed corners. The motivation to do so is to protect the interconnect from the environment (Lee, [86, 81]) and reduce warp due to mismatch in coefficient of thermal expansion of Lee 110 and 130 (Hu, [8]). Re claim 16 , Lee modified above teaches the semiconductor package of claim 15, wherein the first portion and the second portion of the encapsulant include the same material (Lee, 130, fig17, [135]). Re claim 17 , Lee modified above teaches the semiconductor package of claim 14, wherein the fiber layer includes at least one of a carbon fiber (Chiang, [13]) and a glass fiber (Chiang, [13]) . 07-21-aia AIA Claim (s) 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. US 2017/0103951 in view Hu et al. US 2015/0049441 . Re claim 18 , Lee teaches a semiconductor package (fig9 and 10), comprising: a lower redistribution structure (140, fig9, [108]) including a lower redistribution layer (142a/b, fig9, [108]); a semiconductor chip (120, fig9, [90]) disposed on the lower redistribution structure and including connection pads (122, fig9, [90]) electrically connected to the lower redistribution layer; a frame structure (110, fig9, [96]) disposed on the lower redistribution structure and having internal side surfaces (side surface of 110 facing 120, fig9, [96]) surrounding a side surface of the semiconductor chip, external side surfaces (side surface of 110 facing away from 120, fig9, [96]) opposite to the internal side surfaces. Lee does not explicitly show corner surfaces connecting adjacent external side surfaces. Hu teaches corner surfaces (two side surface of each 105a, 100a, 110a and 115a, fig3, [34]) connecting adjacent external side surfaces (side surface of 70 facing away from 75 and overlap with 75, fig3). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lee and Hu to recess the corner of 110 in Lee fig9. The motivation to do so is to reduce warpage (Hu, [9]). Embodiment of Lee fig 9-10 does not explicitly show an encapsulant covering the side surface of the semiconductor chip and the corner surfaces of the frame structure. Lee fig17 and 18 teaches an encapsulant (Lee, 130, fig17, [135]) covering the side surface of the semiconductor chip and the corner surfaces of the frame structure (Lee, fig18). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to cover all exposed surfaces of the interconnection structure 110 with recessed corners and form 110A-E as 70 of Hu with recessed corners. The motivation to do so is to protect the interconnect from the environment (Lee, [86, 81]) and reduce warp due to mismatch in coefficient of thermal expansion of Lee 110 and 130 (Hu, [8]) . 07-21-aia AIA Claim (s) 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. US 2017/0103951 in view Hu et al. US 2015/0049441 and Chiang et al. US 2020/0269556 . Re claim 19 , Lee does not explicitly show the semiconductor package of claim 18, wherein the frame structure includes a fiber layer having first fibers and second fibers arranged to intersect with each other, and an insulating resin layer in which the fiber layer is embedded. Chiang teaches prepreg with a fiber layer (10 and 20, fig1, [13]) having first fibers and second fibers arranged to intersect with each other, and an insulating resin layer (30, fig1, [12]) in which the fiber layer is embedded. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lee in view of Hu and Chiang to form the prepreg with the process of Chiang. The motivation to do so is to achieve both strength and weight reduction and improve yield and production throughput (Chiang, [2, 30-34]). Re claim 20 , Lee modified above teaches the semiconductor package of claim 19, wherein at least a portion of the first and second fibers have at least one end adjacent to the corner surfaces (fiber ends of prepreg located at recessed corners of Lee 110 as shown by Hu fig3) . 07-21-aia AIA Claim (s) 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. US 2017/0103951 in view Hu et al. US 2015/0049441, Chiang et al. US 2020/0269556 and Cok et al. US 2020/0395316 . Re claim 4 , Lee does not explicitly show the semiconductor package of claim 2, wherein the width of the margin region is in a range of 100 μm to 200 μm. Hu teaches the width of the margin region is about the width of the chip width (fig3). Cok teaches die with a width of about 50-100 μm (22, fig4A, [96]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lee modified above and Cok to adjust the width of the margin region to accommodate the die located at the center and the TSV around the die. The motivation to do so is to reduce package size and reduce process cost (Cok, [96]). Allowable Subject Matter 07-43 Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim. Specifically, the limitations are material to the inventive concept of the application in hand to reduce warpage of the chip package by adding encapsulation layer on the recessed corner section with external surface exposed from the encapsulation layer. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOMING LIU whose telephone number is (571)270-0384. The examiner can normally be reached Monday-Friday, 9am-8pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /XIAOMING LIU/Examiner, Art Unit 2812 Application/Control Number: 18/659,703 Page 2 Art Unit: 2812 Application/Control Number: 18/659,703 Page 3 Art Unit: 2812 Application/Control Number: 18/659,703 Page 4 Art Unit: 2812 Application/Control Number: 18/659,703 Page 5 Art Unit: 2812 Application/Control Number: 18/659,703 Page 6 Art Unit: 2812 Application/Control Number: 18/659,703 Page 7 Art Unit: 2812 Application/Control Number: 18/659,703 Page 8 Art Unit: 2812 Application/Control Number: 18/659,703 Page 9 Art Unit: 2812 Application/Control Number: 18/659,703 Page 10 Art Unit: 2812 Application/Control Number: 18/659,703 Page 11 Art Unit: 2812 Application/Control Number: 18/659,703 Page 12 Art Unit: 2812
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