DETAILED ACTION
This office action is in response to the application filed on May 9, 2024. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 9, 2024 is being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2022/0406697) in view of Jung (US 2023/0005828).
With respect to Claim 1, Kim ‘697 shows (Fig. 1,2) most aspects of the current invention including a semiconductor package comprising:
a first dielectric structure (151);
a first pad (CP) in the first dielectric structure;
a first semiconductor chip (130) provided on the first dielectric structure;
a bump (160) electrically connected to the first pad,
wherein the first semiconductor chip includes:
a first substrate (152);
a first chip dielectric layer (135/137) in contact with the first dielectric structure;
a first chip pad (pads 139) in contact with a top surface of the first pad,
wherein the first pad (CP) is provided between the bump (160) and the first chip pad (pads 139) of the first semiconductor chip
Kim ‘697 fails to explicitly disclose wherein the first pad comprises a first conductive layer and a second conductive layer covered by the first conductive layer, and wherein the bump is positioned closer to the first conductive layer than to the second conductive layer.
On the other hand, and in the same field of endeavor, Jung teaches (Fig 1-2) a semiconductor package comprising a first dielectric structure (45), a first pad (5) in the first dielectric structure, a first semiconductor chip (100) provided on the first dielectric structure, a bump (150) electrically connected to the first pad, wherein the first pad comprises a first conductive layer (4a) and a second conductive layer (4b) covered by the first conductive layer, wherein the bump (150) is positioned closer to the first conductive layer than to the second conductive layer. Jung teaches the first conductive layer is used as a seed layer and furthermore at least one of the conductive material of the first conductive layer and/or second conductive layer may be selected such that the second conductive layer does not delaminate from the first conductive layer due to lattice mismatch between the conductive materials and/or such that the free energy of nucleation (and/or crystal growth) is greater than a neighboring material (par 28)
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein the first pad comprises a first conductive layer and a second conductive layer covered by the first conductive layer, and wherein the bump is positioned closer to the first conductive layer than to the second conductive layer, in the device of Kim ‘697, as taught by Jung, because the first conductive layer is used as a seed layer and furthermore at least one of the conductive material of the first conductive layer and/or second conductive layer may be selected such that the second conductive layer does not delaminate from the first conductive layer due to lattice mismatch between the conductive materials and/or such that the free energy of nucleation (and/or crystal growth) is greater than a neighboring material.
With respect to Claim 2, Jung teaches (Fig 1-2) wherein conductive materials of the first conductive layer and conductive materials of the second conductive layer are different.
Claims 1-5, 11, 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2022/0406697) in view of Bae (US 2022/0415835)
With respect to Claim 1, Kim ‘697 shows (Fig. 1,2) most aspects of the current invention including a semiconductor package comprising:
a first dielectric structure (151);
a first pad (CP) in the first dielectric structure;
a first semiconductor chip (130) provided on the first dielectric structure;
a bump (160) electrically connected to the first pad,
wherein the first semiconductor chip includes:
a first substrate (152);
a first chip dielectric layer (135/137) in contact with the first dielectric structure;
a first chip pad (pads 139) in contact with a top surface of the first pad,
wherein the first pad (CP) is provided between the bump (160) and the first chip pad (pads 139) of the first semiconductor chip
Kim ‘697 fails to explicitly disclose wherein the first pad comprises a first conductive layer and a second conductive layer covered by the first conductive layer, and wherein the bump is positioned closer to the first conductive layer than to the second conductive layer.
On the other hand, and in the same field of endeavor, Bae teaches (Fig 1-2b) a semiconductor package comprising a first dielectric structure (200), a first pad (251) in the first dielectric structure, a first semiconductor chip (100) provided on the first dielectric structure, a bump (290) electrically connected to the first pad, wherein the first pad (251) comprises a first conductive layer (251a) and a second conductive layer (251b) covered by the first conductive layer, wherein the bump (290) is positioned closer to the first conductive layer than to the second conductive layer. Bae teaches the first conductive layer is used as a barrier layer and furthermore may limit and/or prevent a metallic material of the second conductive layer from diffusing toward the fourth base dielectric layer in the dielectric structure (par 42).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein the first pad comprises a first conductive layer and a second conductive layer covered by the first conductive layer, and wherein the bump is positioned closer to the first conductive layer than to the second conductive layer in the device of Kim ‘697, as taught by Bae because the first conductive layer is used as a barrier layer and furthermore may limit and/or prevent a metallic material of the second conductive layer from diffusing toward the fourth base dielectric layer in the dielectric structure.
With respect to Claim 2, Bae teaches (Fig 1-2b) wherein conductive materials of the first conductive layer and conductive materials of the second conductive layer are different.
With respect to Claim 3, Bae teaches (Fig 1-2b) wherein the first conductive layer (251a) comprises: a first part (horizontal part) in contact with the bottom surface of the second conductive layer; and a second part (vertical part) in contact with the first chip pad of the first semiconductor chip, wherein the second part covers the second conductive layer.
With respect to Claim 4, Bae teaches (Fig 1-2b) wherein the first part (horizontal part) of the first conductive layer is between the bump and the second conductive layer.
With respect to Claim 5, Bae teaches (Fig 1-2b) wherein an inner sidewall of the second part (vertical part) of the first conductive layer is in contact with an outer sidewall of the second conductive layer.
With respect to Claim 11, Kim ‘697 shows (Fig. 1,2) most aspects of the current invention including a semiconductor package comprising:
a first dielectric structure (151);
a first pad (CP) in the first dielectric structure;
a first semiconductor chip (130) provided on the first dielectric structure;
a bump (160) electrically connected to the first pad,
wherein the first semiconductor chip includes:
a first substrate (152);
a first chip dielectric layer (135/137) in contact with the first dielectric structure;
a first chip pad (pads 139) in contact with a top surface of the first pad,
Kim ‘697 fails to explicitly disclose wherein the first pad comprises a first conductive layer and a second conductive layer covered by the first conductive layer, wherein the first conductive layer comprises a top surface and a bottom surface that are opposite to each other, wherein the top surface of the first conductive layer is in contact with the first chip pad of the first semiconductor chip, and wherein an area at the bottom surface of the first conductive layer is greater than an area at the top surface of the first conductive layer.
On the other hand, and in the same field of endeavor, Bae teaches (Fig 1-2b) a semiconductor package comprising a first dielectric structure (200), a first pad (251) in the first dielectric structure, a first semiconductor chip (100) provided on the first dielectric structure, a bump (290) electrically connected to the first pad, wherein the first pad (251) comprises a first conductive layer (251a) and a second conductive layer (251b) covered by the first conductive layer, wherein the first conductive layer comprises a top surface (top surface of 251a) and a bottom surface (bottom surface of 251a) that are opposite to each other, wherein the top surface of the first conductive layer is in contact with the first chip pad of the first semiconductor chip, and wherein an area at the bottom surface of the first conductive layer is greater than an area at the top surface of the first conductive layer. Bae teaches the first conductive layer is used as a barrier layer and furthermore may limit and/or prevent a metallic material of the second conductive layer from diffusing toward the fourth base dielectric layer in the dielectric structure (par 42).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein the first pad comprises a first conductive layer and a second conductive layer covered by the first conductive layer, wherein the first conductive layer comprises a top surface and a bottom surface that are opposite to each other, wherein the top surface of the first conductive layer is in contact with the first chip pad of the first semiconductor chip, and wherein an area at the bottom surface of the first conductive layer is greater than an area at the top surface of the first conductive layer in the device of Kim ‘697, as taught by Bae because the first conductive layer is used as a barrier layer and furthermore may limit and/or prevent a metallic material of the second conductive layer from diffusing toward the fourth base dielectric layer in the dielectric structure.
With respect to Claim 13, Bae teaches (Fig 1-2b) wherein the first conductive layer comprises at least one selected from tantalum nitride, tantalum, titanium nitride, and titanium, and the second conductive layer comprises copper (par 44-45)
With respect to Claim 14, Bae teaches (Fig 1-2b) wherein the second conductive layer comprises a top surface (top surface of 251b) in contact with the first chip pad, wherein an area at the top surface of the second conductive layer is greater than the area at the top surface of the first conductive layer.
With respect to Claim 15, Bae teaches (Fig 1-2b) wherein a width of the first chip pad may be smaller or equal to a width of the first pad (par 53).
Regarding claim 15, the courts have held that differences in widths will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such widths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of the claimed widths, and similar widths are commonly known in the art, (see e.g. Bae), it would have been obvious to one of the ordinary skill in the art to use these values in the device of Kim ‘697.
Criticality: The specification contains no disclosure of either the critical nature of the claimed widths or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
Claims 6-8 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2022/0406697) in view of Bae (US 2022/0415835) and in further view of Kim (US 2022/0165698)
With respect to Claim 6, Kim ‘697 in view of Bae shows most aspects of the current invention. Kim ‘697 shows (Fig. 1,2) wherein the first dielectric structure (151) comprises a first dielectric layer (151b) and a second dielectric layer (151a) on the first dielectric layer, wherein the second dielectric layer is in contact with the first chip dielectric layer of the first semiconductor chip, and wherein the first dielectric layer and a second dielectric layer may include an inorganic material. However, the combination of references do not show wherein the first dielectric layer and the second dielectric layer comprise different dielectric materials from each other.
On the other hand, and in the same field of endeavor, Kim ‘698 teaches (Fig 1) a semiconductor package comprising a first dielectric structure (111), a first pad (114) in the first dielectric structure, a first semiconductor chip (120) provided on the first dielectric structure, a bump (140) electrically connected to the first pad, wherein the first dielectric structure (111) comprises a first dielectric layer (111a) and a second dielectric layer (111b) on the first dielectric layer, wherein the first dielectric layer and the second dielectric layer comprise different dielectric materials from each other (see par 23). Kim ‘698 teaches one of the first dielectric layer or the second dielectric layer may include an insulating resin and one of the first dielectric layer or the second dielectric layer may include a photosensitive resin such as a photoimageable dielectric (PID) resin, which are materials used to support the wiring layers in the dielectric structure (par 23).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein the first dielectric layer and the second dielectric layer comprise different dielectric materials from each other in the device of Kim ‘697 and Bae, as taught by Kim ‘698, because one of the first dielectric layer or the second dielectric layer may include an insulating resin and one of the first dielectric layer or the second dielectric layer may include a photosensitive resin such as a photoimageable dielectric (PID) resin, which are materials used to support the wiring layers in the dielectric structure.
With respect to Claim 7, Kim ‘697 shows (Fig. 1,2) wherein the first dielectric layer comprises silicon oxide, and the second dielectric layer comprises silicon nitride, silicon carbonitride, or silicon carbon oxynitride (par 28).
With respect to Claim 8, Kim ‘697 shows (Fig. 1,2) wherein a dielectric material included in the first chip dielectric layer (135/137) is identical to the dielectric material of the second dielectric layer (111b) (par 26 and 28)
With respect to Claim 12, Kim ‘697 in view of Bae shows most aspects of the current invention. Bae teaches (Fig 1-2b) wherein the first pad (251) comprises a first conductive layer (251a) and a second conductive layer (251b) covered by the first conductive layer, wherein the first conductive layer surrounds the second conductive layer. However, the combination of references do not show wherein the top surface of the first conductive layer has a ring shape when viewed in plan.
However, it is noted that the specification fails to provide teachings about the criticality of having the top surface of the first conductive layer has a ring shape when viewed in plan, as claimed in the instant application.
Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the first conductive layer disclosed by Kim ‘698 as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, as the particular ring shape of the first conductive layer claimed by applicant is nothing more than one of numerous conductive layer shapes that a person having ordinary skill in the art will find obvious to provide using routine experimentation based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976).
On the other hand, and in the same field of endeavor, Kim ‘698 teaches (Fig 1) a semiconductor package comprising a first dielectric structure (111), a first pad (114) in the first dielectric structure, wherein the top surface of the first pad has a ring shape when viewed in plan, which is typically used in the semiconductor packaging art to provide external connections from a semiconductor chip to an external device outside the package.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein the top surface of the first conductive layer has a ring shape when viewed in plan in the device of Kim ‘697 and Bae, because conductive pads are well-known in the semiconductor packaging art for their use as means to provide external connections from a semiconductor chip to an external device outside the package, as taught by Kim ‘698, and implementing an electrical connection structure for its conventional use would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2022/0406697) in view of Bae (US 2022/0415835) and in further view of Lee (US 2021/0358875).
With respect to Claim 9, Kim ‘697 in view of Bae shows most aspects of the current invention. However, the combination of references do not show further comprising a second dielectric structure spaced apart from the first dielectric structure across the first semiconductor chip; a second pad in the second dielectric structure; and a gap-fill layer between the first dielectric structure and the second dielectric structure, wherein the first semiconductor chip comprises a through via that electrically connects the second pad and the first semiconductor chip to each other.
On the other hand, and in the same field of endeavor, Lee teaches (Fig 1-2) a semiconductor package comprising a first dielectric structure (130 including insulating layers 131O,132O), a first pad (conductive layer 132L) in the first dielectric structure, a first semiconductor chip (140) provided on the first dielectric structure, a bump (110) electrically connected to the first pad, and further comprising a second dielectric structure (BO1) spaced apart from the first dielectric structure across the first semiconductor chip; a second pad (BP1) in the second dielectric structure; and a gap-fill layer (MD1) between the first dielectric structure and the second dielectric structure, wherein the first semiconductor chip comprises a through via (145) that electrically connects the second pad and the first semiconductor chip to each other. Lee teaches the through vias (TSVs) penetrate the substrate to provide an electrical connection between the second semiconductor chip and the first pad (conductive layer 132L) in the first dielectric structure (130 including insulating layers 131O,132O) (par 44-46).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of a second dielectric structure spaced apart from the first dielectric structure across the first semiconductor chip; a second pad in the second dielectric structure; and a gap-fill layer between the first dielectric structure and the second dielectric structure, wherein the first semiconductor chip comprises a through via that electrically connects the second pad and the first semiconductor chip to each other in the device of Kim ‘697 and Bae, as taught by Lee because the through vias (TSVs) penetrate the substrate to provide an electrical connection between the second semiconductor chip and the first pad (conductive layer 132L) in the first dielectric structure (130 including insulating layers 131O,132O).
With respect to Claim 10, Lee teaches (Fig 1-2) further comprising a second semiconductor chip (150) in contact with the second dielectric structure, wherein the second semiconductor chip comprises: a second substrate (151); a second chip dielectric layer (BO2) in contact with the second dielectric structure; and a second chip pad (BP2) in contact with the second pad.
Claims 16,18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2022/0406697) in view of Bae (US 2022/0415835) and in further view of Jang (US 2024/0038728).
With respect to Claim 16, Kim ‘697 in view of Bae shows most aspects of the current invention. However, the combination of references do not show further comprising a plurality of alignment keys in the first dielectric structure, wherein the first pad is between the alignment keys.
On the other hand, and in the same field of endeavor, Jang teaches (Fig 6-8) a semiconductor package comprising a first dielectric structure (364), a first pad (354) in the first dielectric structure, and a first semiconductor chip (100A) in contact with the first dielectric structure, and further comprising a plurality of alignment keys (357/AK) in the first dielectric structure, wherein the first pad is between the alignment keys. Jang teaches doing so to form a plurality of alignment keys using a metal oxide film which is configured to be in direct contact with the molded layer/gap fill layer, thereby increasing bonding strength between the molded layer/gap fill layer and the first dielectric structure (par 37,76).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of a plurality of alignment keys in the first dielectric structure, wherein the first pad is between the alignment keys in the device of Kim ‘697 and Bae, as taught by Jang, to form a plurality of alignment keys using a metal oxide film which is configured to be in direct contact with the molded layer/gap fill layer, thereby increasing bonding strength between the molded layer/gap fill layer and the first dielectric structure.
With respect to Claim 18, Jang teaches (Fig 6-8) further comprising a gap-fill layer (180) that covers the first semiconductor chip (100A), wherein the alignment keys are in contact with the gap-fill layer.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2022/0406697) in view of Jang (US 2024/0038728) and in further view of Bae (US 2022/0415835).
With respect to Claim 19, Kim ‘697 shows (Fig. 1,2) most aspects of the current invention including a semiconductor package comprising:
a first dielectric structure (151);
a first pad (CP) in the first dielectric structure;
a first semiconductor chip (130) in contact with the first dielectric structure;
a bump (160) electrically connected to the first pad,
a second dielectric structure (171) spaced apart from the first dielectric structure across the first semiconductor chip
a first gap-fill layer (140) between the first dielectric structure and the second dielectric structure
a second semiconductor chip (181) in contact with the second dielectric structure
a second gap-fill layer (185) that surrounds the second semiconductor chip,
Kim ‘697 fails to explicitly disclose a plurality of key patterns in the first dielectric structure, and wherein the first pad includes a first conductive layer and a second conductive layer in the first conductive layer, wherein the first conductive layer includes: a first part between the bump and the second conductive layer; and a second part that surrounds the second conductive layer, wherein the first part of the first conductive layer includes a surface in contact with a bottom surface of the second conductive layer, and wherein a top surface of the second part of the first conductive layer and a top surface of the second conductive layer are in contact with the first chip pad.
On the other hand, and in the same field of endeavor, Jang teaches (Fig 6-8) a semiconductor package comprising a first dielectric structure (364), a first pad (354) and a plurality of key patterns (357/AK) in the first dielectric structure, and a first semiconductor chip (100A) in contact with the first dielectric structure. Jang teaches doing so to form a plurality of alignment keys using a metal oxide film which is configured to be in direct contact with the molded layer/gap fill layer, thereby increasing bonding strength between the molded layer/gap fill layer and the first dielectric structure (par 37,76).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of a plurality of key patterns in the first dielectric structure in the device of Kim ‘697, as taught by Jang, to form a plurality of alignment keys using a metal oxide film which is configured to be in direct contact with the molded layer/gap fill layer, thereby increasing bonding strength between the molded layer/gap fill layer and the first dielectric structure.
However, Jang fails to explicitly disclose wherein the first pad includes a first conductive layer and a second conductive layer in the first conductive layer, wherein the first conductive layer includes: a first part between the bump and the second conductive layer; and a second part that surrounds the second conductive layer, wherein the first part of the first conductive layer includes a surface in contact with a bottom surface of the second conductive layer, and wherein a top surface of the second part of the first conductive layer and a top surface of the second conductive layer are in contact with the first chip pad.
On the other hand, and in the same field of endeavor, Bae teaches (Fig 1-2b) a semiconductor package comprising a first dielectric structure (200), a first pad (251) in the first dielectric structure, a first semiconductor chip (100) provided on the first dielectric structure, a bump (290) electrically connected to the first pad, wherein the first pad (251) comprises a first conductive layer (251a) and a second conductive layer (251b) in the first conductive layer, wherein the first conductive layer includes: a first part (horizontal part) between the bump and the second conductive layer; and a second part (vertical part) that surrounds the second conductive layer, wherein the first part of the first conductive layer includes a surface in contact with a bottom surface of the second conductive layer, and wherein a top surface (top surface of 251a) of the second part of the first conductive layer and a top surface (top surface of 251b) of the second conductive layer are in contact with the first chip pad. Bae teaches the first conductive layer is used as a barrier layer and furthermore may limit and/or prevent a metallic material of the second conductive layer from diffusing toward the fourth base dielectric layer in the dielectric structure (par 42).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein the first pad includes a first conductive layer and a second conductive layer in the first conductive layer, wherein the first conductive layer includes: a first part between the bump and the second conductive layer; and a second part that surrounds the second conductive layer, wherein the first part of the first conductive layer includes a surface in contact with a bottom surface of the second conductive layer, and wherein a top surface of the second part of the first conductive layer and a top surface of the second conductive layer are in contact with the first chip pad in the device of Kim ‘697 and Jang, as taught by Bae because the first conductive layer is used as a barrier layer and furthermore may limit and/or prevent a metallic material of the second conductive layer from diffusing toward the fourth base dielectric layer in the dielectric structure.
With respect to Claim 20, Jang teaches (Fig 6-8) wherein top surfaces of the key patterns are in contact with a bottom surface of a first gap-fill layer (180).
Allowable Subject Matter
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/Q.A.B/ Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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