DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention I, claims 1-8 and 15-20, in the reply filed on 06/19/2026 is acknowledged.
Claims 9-14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/19/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang (US 2011/0100697).
Regarding claim 1, Yang discloses, in FIG. 11 and in related text, a semiconductor structure comprising:
a first metal level in a first dielectric layer (204), the first metal level including a metal line (206) (see Yang, [0020], [0029]);
a second metal level (including metal material 234) over the first metal level and in a second dielectric layer (214), the second metal level including a trench (230) directly over a via (218) (see Yang, [0021], [0045], [0058]); and
a dielectric liner (222) lining sidewalls of the via, the dielectric liner being absent at a bottom and a top of the via (see Yang, [0042]: dielectric liner 222 includes silicon oxide, silicon nitride or silicon carbide).
Claims 1-5 and 8 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chung (US 2023/0154791).
Regarding claim 1, a semiconductor structure comprising:
a first metal level in a first dielectric layer (301), the first metal level including a metal line (308) (see Chung, [0036]);
a second metal level (including metal material 332, 334) over the first metal level and in a second dielectric layer (316), the second metal level including a trench (320 in FIG. 3A) directly over a via (318 in FIG. 3A) (see Chung, [0039], [0045]); and
a dielectric liner (328) lining sidewalls of the via, the dielectric liner being absent at a bottom and a top of the via (see Chung, [0037], [0043]: dielectric liner 328 include metal oxide such as hafnium oxide).
Regarding claim 2, Chung discloses the structure of claim 1.
Chung discloses wherein the dielectric liner (328) further lines sidewalls of the trench and a portion of a bottom of the trench (320), the dielectric liner being in direct contact with the second dielectric layer (316) (see Chung, FIG. 3C, [0043]).
Regarding claim 3, Chung discloses the structure of claim 1.
Chung discloses wherein the dielectric liner (328) conformally lines sidewalls of the trench; a portion of a bottom of the trench (320); and the sidewalls of the via (318) (see Chung, FIG. 3C, [0043]), and wherein the dielectric liner (328, hafnium oxide) has a dielectric constant that is higher than a dielectric constant of the first dielectric layer (301, low-k dielectric) and the second dielectric layer (316, low-k dielectric) (see Chung, [0036]-[0037], [0039], [0043]: low-k dielectric has dielectric constant value less that of silicon oxide, or 3.9; metal oxide such as hafnium oxide has dielectric constant value higher than that of silicon oxide; see, for example, US 2003/0227033, [0034]).
Regarding claim 4, Chung discloses the structure of claim 1.
Chung discloses wherein the trench (320) and the via (318) are formed through a dual-damascene process to have a common conductive core (332, 334) (see Chung, FIGS. 3A and 3E, [0039], [0045]).
Regarding claim 5, Chung discloses the structure of claim 4.
Chung discloses a metallic liner (330) lining a surface of the common conductive core (332, 334) of the trench and the via of the second metal level (see Chung, FIG. 3E, [0043]: metallic liner 330 include Co or Ru).
Regarding claim 8, Chung discloses the structure of claim 1.
Chung discloses one or more etch- stop layers (314) between the first dielectric layer (301) and the second dielectric layer (316), wherein the etch-stop layers are either aluminum-oxide or aluminum-nitride (see Chung, FIG. 3E, [0038]).
Claims 1-2 and 4-5 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Murray (US 2016/0358859).
Regarding claim 1, Murray discloses, in FIG. 6 and in related text, a semiconductor structure comprising:
a first metal level in a first dielectric layer (25), the first metal level including a metal line (20) (see Murray, [0022]);
a second metal level (including metal fill 45) over the first metal level and in a second dielectric layer (15a), the second metal level including a trench (opening 10 with width W1 in FIG. 1) directly over a via (opening 10 with width W2 in FIG. 1) (see Murray, [0026]-[0027], [0037]); and
a dielectric liner (30) lining sidewalls of the via, the dielectric liner being absent at a bottom and a top of the via (see Murray, FIG. 6, [0028]: dielectric liner includes silicon oxide or silicon carbide).
Regarding claim 2, Murray discloses the structure of claim 1.
Murray discloses wherein the dielectric liner (30) further lines sidewalls of the trench and a portion of a bottom of the trench (opening 10), the dielectric liner being in direct contact with the second dielectric layer (15a) (see Murray, FIG. 4, [0028]).
Regarding claim 4, Murray discloses the structure of claim 1.
Murray discloses wherein the trench and the via (opening 10) are formed through a dual-damascene process to have a common conductive core (45) (see Murray, FIGS. 1 and 6, [0027], [0037]).
Regarding claim 5, Murray discloses the structure of claim 4.
Murray discloses a metallic liner (35) lining a surface (sidewalls) of the common conductive core (45) of the trench and the via of the second metal level (see Murray, FIG. 6, [0030]: metallic liner 35 includes titanium or titanium nitride).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Murray (US 2016/0358859) in view of Yang (US 2011/0100697).
Regarding claim 15, Murray discloses, in FIG. 6 and in related text, an interconnect structure comprising:
a first metal level in a first dielectric layer (25), the first metal level including a metal line (20) (see Murray, [0022]);
a second metal level (including metal fill 45) over the first metal level in a second dielectric layer (15a), the second metal level including a trench (opening 10 with width W1 in FIG. 1) directly over a via (opening 10 with width W2 in FIG. 1) (see Murray, [0026]-[0027], [0037]); and
a dielectric liner (30) lining sidewalls of the via, sidewalls of the trench, and a bottom of the trench;
wherein the dielectric liner is absent at a bottom of the via such that the via is conductively connected to the metal line of the first metal level (see Murray, FIG. 6, [0028], [0039]: dielectric liner includes silicon oxide or silicon carbide).
Murray does not explicitly via such that the via is conductively connected to the metal line of the first metal level via a metallic liner.
Yang teaches such that the via (including conductive material 234) is conductively connected to the metal line (206) of the first metal level via a metallic liner (232) (see Yang, FIG. 11, [0053], [0058]).
Murray and Yang are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Murray with the features of Yang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Murray to include such that the via is conductively connected to the metal line of the first metal level via a metallic liner, as taught by Yang, to provide a diffusion barrier and to provide a gouging feature for improved wiring reliability (see Yang, [0018], [0053], [0058].
Regarding claim 16, Murray in view of Yang teaches the structure of claim 15.
Murray discloses wherein the dielectric liner (30) is a conformal dielectric liner of moderate or high-k dielectric material, the moderate or high- k dielectric material being selected from a group consisting of silicon-nitride, silicon-oxide, silicon-carbide, hafnium-oxide, and lanthanum-oxide (see discussion on claim 15 above).
Regarding claim 17, Murray in view of Yang teaches the structure of claim 15.
Murray discloses wherein the trench and the via (opening 10) are formed through a dual-damascene process such that the dielectric liner is absent between the trench and the via (see Murray, FIGS. 1 and 6, [0027], [0037]).
Regarding claim 18, Murray in view of Yang teaches the structure of claim 15.
Yang teaches a metallic liner (232) lining the trench and the via (see Yang, FIG. 11, [0053]), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 15.
Regarding claim 19, Murray in view of Yang teaches the structure of claim 18.
Yang teaches wherein a portion of the metallic liner (232) covering a lower portion of the via is vertically underneath the dielectric liner (222) (see Yang, FIG. 11, [0053]), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 15.
Regarding claim 20, Murray in view of Yang teaches the structure of claim 18.
Yang teaches wherein a lower portion of the via has an outward edge (outward edge of metallic liner 232 under dielectric liner 222) (see Yang, FIG. 11), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 15.
Allowable Subject Matter
Claims 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of records, individually or in combination, do not disclose nor teach “wherein a portion of the metallic liner lining a lower portion of the via fills a notch vertically underneath the dielectric liner, wherein the notch is between the dielectric liner and an etch-stop layer above the first dielectric layer” in combination with other limitations as recited in claim 6.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIH TSUN A CHOU whose telephone number is (408)918-7583. The examiner can normally be reached M-F 8:00-16:00 Arizona Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHIH TSUN A CHOU/Primary Examiner, Art Unit 2811
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