Prosecution Insights
Last updated: May 29, 2026
Application No. 18/659,932

SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS USING THE SAME

Non-Final OA §103
Filed
May 09, 2024
Priority
Jul 13, 2023 — RE 10-2023-0091111
Examiner
PERSAUD, DEORAM
Art Unit
2882
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
579 granted / 755 resolved
+8.7% vs TC avg
Moderate +12% lift
Without
With
+11.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
20 currently pending
Career history
792
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
63.2%
+23.2% vs TC avg
§102
28.3%
-11.7% vs TC avg
§112
0.8%
-39.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 755 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ho et al. [US 20060154185 A1] in view of Uraguchi et al. [US 5,571,644 A]. Regarding claims 1, 9-11, 16 and 17, Ho et al. discloses a substrate processing method (Fig. 3), comprising: forming a layer on a substrate (paragraph [0016] teaches a dielectric insulating layer); forming a photoresist layer on the layer (301, paragraph [0026] teaches overlying photoresist layer); exposing the photoresist layer using an exposure mask (303, paragraph [0026] teaches photoresist is exposed with light through a mask); performing a first post-exposure baking process on the photoresist layer (305, paragraph [0026] teaches a first baking step); developing the photoresist layer using a first developing solution (307, paragraph [0026] teaches wherein photoresist layer is developed); performing a second post-exposure baking process on the photoresist layer (309, paragraph [0026] teaches a second baking step); developing the photoresist layer using a second developing solution (311, paragraph [0026] teaches a second development process); forming a photoresist pattern by performing a hard baking process on the photoresist layer (paragraph [0025] teaches the hard baking process); and partially removing the layer by performing an etching process using the photoresist pattern as an etching mask (313, paragraph [0026] teaches dry etching process). Ho et al. does not teach a first developing solution having a first temperature and a second developing solution having a second temperature different from the first temperature. However, Uraguchi et al. discloses a resist developing apparatus has a plurality of developing solution containers each provided with a temperature regulator (Fig. 1), wherein the same kind of developing solutions at different temperatures or different kinds of developing solutions are provided for development. (Col. 1 lines 55-60 teaches a plurality of developing solution containers and set to different temperatures for making possible various types of development processes). Therefore, it would have been obvious to one of ordinary skill in the art to provide a first developing solution having a first temperature and a second developing solution having a second temperature different from the first temperature, as taught by Uraguchi et al. in the method of Ho et al. because such a modification makes possible various types of development processes, For example, if developing solution at a low temperature is used, the resist profile can be improved. If developing solution at a high temperature is used, the time required for the development process can be shortened (Col. 2 lines 65-67 – Col. 3 lines 1-4 of Uraguchi et al.). Regarding claims 2, 15 and 18, Ho et al. in view of Uraguchi et al. discloses wherein after the developing the photoresist layer using the first developing solution, the photoresist layer has a first critical dimension, and after the developing the photoresist layer using the second developing solution, the photoresist layer has a second critical dimension greater than the first critical dimension (in the combination of Ho et al. and Uraguchi et al. optimization of the temperature and the developer results in a second critical dimension greater than the first critical dimension, paragraph [0026] teaches having predetermined critical dimensions and Col. 4 lines 26-33 of Uraguchi et al. teaches wherein the development process to obtain a high precision profile). Regarding claim 3, Ho et al. discloses wherein the performing the first post-exposure baking process, the developing the photoresist layer using the first developing solution, the performing the second post-exposure baking process, and the developing the photoresist layer using the second developing solution are sequentially performed (as shown in Fig. 3, see also paragraph [0026] teaches the development and baking process). Regarding claims 4, 5 and 14, Ho et al. discloses wherein the first post-exposure baking process is performed at a third temperature, and the second post-exposure baking process is performed at a fourth temperature, lower than the third temperature, wherein the fourth temperature is within a range of 50° C. to 150° C, wherein the first post-exposure baking process is performed at a third temperature, and the second post-exposure baking process is performed at a fourth temperature, wherein the fourth temperature is within a range of 50% to 80% of the third temperature (paragraphs [0016]-[0020] baking temperatures of 60° C. to 140° C). Regarding claims 6, 7, 12, 13 and 20, Uraguchi et al. discloses wherein the first temperature is within a range of 10° C. to 25° C, wherein the second temperature is within a range of 20° C. to 40° C, wherein the second temperature is higher than the first temperature, wherein the first temperature is within a range of 30% to 150% of room temperature, and the second temperature is within a range of 50% to 200% of room temperature (Col. 3 lines 40-47 and Col. 5 lines 1-11 teaches the temperature of the developing solution is set to an optional value). Regarding claims 8 and 19, Ho et al. in view of Uraguchi et al. discloses wherein after developing the photoresist layer using the first developing solution, the photoresist layer has a first line edge roughness, and after developing the photoresist layer using the second developing solution, the photoresist layer has a second line edge roughness, equal to or smaller than the first line edge roughness (in the combination of Ho et al. and Uraguchi et al. optimization of the temperature and the developer results in a second line edge roughness, equal to or smaller than the first line edge roughness, paragraph [0026] teaches having predetermined critical dimensions and Col. 4 lines 26-33 of Uraguchi et al. teaches wherein the development process to obtain a high precision profile). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEORAM PERSAUD whose telephone number is (571)270-5476. The examiner can normally be reached M-F 8AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Minh-Toan Ton can be reached at 571-272-2303. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DEORAM PERSAUD/Primary Examiner, Art Unit 2882
Read full office action

Prosecution Timeline

May 09, 2024
Application Filed
Jan 10, 2026
Non-Final Rejection (signed) — §103
Feb 18, 2026
Non-Final Rejection mailed — §103
Apr 07, 2026
Examiner Interview Summary
Apr 07, 2026
Applicant Interview (Telephonic)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12638782
METHOD OF DETERMINING A SAMPLING SCHEME, ASSOCIATED APPARATUS AND COMPUTER PROGRAM
3y 7m to grant Granted May 26, 2026
Patent 12638766
EUV PELLICLE WITH STRUCTURED VENTILATION FRAME
3y 1m to grant Granted May 26, 2026
Patent 12631978
SUBSTRATE PROCESSING SYSTEM AND SUBSTRATE PROCESSING METHOD, AND DEVICE MANUFACTURING METHOD
2y 4m to grant Granted May 19, 2026
Patent 12631970
IMAGING VIA ZEROTH ORDER SUPPRESSION
2y 5m to grant Granted May 19, 2026
Patent 12625433
SPATIAL LIGHT MODULATION UNIT AND EXPOSURE APPARATUS
2y 4m to grant Granted May 12, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
88%
With Interview (+11.8%)
2y 9m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 755 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month