Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/4/25 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2016/0079994) in view of Xu et al. (US 7,834,796).
With regard to claim 1, Lee discloses:
an apparatus, comprising: a capacitive digital-to-analog converter (CDAC) that comprises: a first capacitor array (705 Fig. 16), the first capacitor array comprising a first plurality of unary-weighted capacitors (711 Fig. 16) having the same capacitor value and a first plurality of binary-weighted capacitors (712 Fig. 16) ( para 103 Most Significant Bit (MSB) DACs 711 have 14 unary weighted capacitors whose size is 64 and are controlled by the output of the flash ADC. LSB DACs 712 are composed of binary weighted capacitors (size of 1 to 64) and controlled by a SAR logic block 703.; a comparator, wherein a first input of the comparator is connected to an output voltage of the CDAC, and wherein a second input of the comparator is selectively connected to a sampled analog input; and a successive approximation register (SAR) logic (703 Fig. 16) configured to control the CDAC and the comparator to perform a successive approximation conversion of the analog input into a digital output (Fig. 16) .
Lee fails to disclose:
a comparator, wherein a first input of the comparator is connected to an output voltage of the CDAC, and wherein a second input of the comparator is selectively connected to a sampled analog input.
Xu discloses in Figure 2;
A SAR analog to digital converter that comprises comparator (202) whose first input is coupled to a capacitive DAC and a second input is coupled a sample and hold circuit. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the application to have applied the teachings of Xu in the SAR ADC of Lee for the benefit to speed up the conversion process and reduce laency so critical in SAR ADC converters.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yuan (US 2017/0033800).
An apparatus, comprising: a first capacitor array comprising a first plurality of binary-weighted capacitors (110 Fig. 1); a second capacitor array comprising a second plurality of binary-weighted capacitors (120 Fig. 2); a comparator (140 Fig. 2), wherein a first input of the comparator is connected to an output voltage of the first capacitor array, and wherein a second input of the comparator is connected to an output voltage of the second capacitor array (comparators 140 inputs are connected to output of the array of capacitors) ; and a successive approximation register (SAR) logic (logic circuit 160 Fig. 1) configured to control the first capacitor array, the second capacitor array, and the comparator to perform a successive approximation conversion of an analog input into a digital output.
Allowable Subject Matter
Claims 2-10 and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 11-15 are allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEGUY JEAN PIERRE whose telephone number is (571) 272-1803. The examiner can normally be reached from 8:00-6:30 PM Monday-Thursday. The examiner’s fax phone number is (571) 273-1803. The Examiner email address is peguy.jeanpierre@uspto.gov. If attempts to reach the Examiner are unsuccessful, the Examiner’s supervisor Dameon E. Levi can be reached at (571) 272-2105.
/PEGUY JEAN PIERRE/Primary Examiner, Art Unit 2845