DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species I in the reply filed on 7/29/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 6, 7, 19 and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/29/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 8-10, and 12-16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by HASEGAWA (US PG Pub 2024/0304607, hereinafter Hasegawa).
Regarding claim 1, figure 1 of Hasegawa discloses a semiconductor package comprising:
a substrate (10) extending in a first direction and a second direction intersecting the first direction;
a first spacer (lowermost 20) disposed on the substrate;
a first semiconductor chip stack (20) disposed on the first spacer, the first semiconductor chip stack includes a plurality of semiconductor chips stacked in a third direction intersecting the first direction and the second direction;
a second spacer (lowermost 30) disposed on the substrate, the second spacer is spaced apart from the first spacer in the first direction;
a second semiconductor chip stack (30) disposed on the second spacer, the second semiconductor chip stack includes a plurality of semiconductor chips stacked in the third direction; and
a mold layer (91) integrally covering the first semiconductor chip stack and the second semiconductor chip stack, the mold layer is in direct contact with side surfaces of the first spacer and side surfaces of the second spacer,
wherein the first semiconductor chip stack and the second semiconductor chip stack are spaced apart from each other in the first direction, and
a width of the first spacer in the first direction is greater than a width of the second spacer in the first direction.
Regarding claim 2, figure 1 of Hasegawa discloses a thickness of the first spacer (lowermost 20) in the third direction is less than a thickness of the second spacer (lowermost 30) in the third direction.
Regarding claim 3, figure 1 of Hasegawa discloses the first semiconductor chip stack comprises a first semiconductor chip (20) disposed on an upper side of the first spacer;
the second semiconductor chip stack comprises a second semiconductor chip (30) disposed on an upper side of the second spacer; and
a thickness of the first semiconductor chip in the third direction is equal to a thickness of the second semiconductor chip in the third direction.
Regarding claim 4, figure 1 of Hasegawa discloses a first adhesive layer (21) between the first semiconductor chip and the first spacer; and
a second adhesive layer (31) between the second semiconductor chip and the second spacer.
Regarding claim 5, figure 1 of Hasegawa discloses a height of an upper side of the first semiconductor chip (20) is greater than a height of a lower side of the second semiconductor chip (30) with respect to the upper side of the substrate (10).
Regarding claim 8, figure 1 of Hasegawa discloses a controller (40) disposed between the first spacer and the second spacer and disposed on the substrate (10), wherein the substrate comprises a wiring structure (¶ 47-48) including a first passivation layer and a second passivation layer spaced apart from each other in the third direction, a first wiring layer in the first passivation layer, and a second wiring layer in the second passivation layer,
the first wiring layer comprises a first upper pad and a second upper pad electrically connected to the first semiconductor chip stack through a first bonding wire (81), a third upper pad and a fourth upper pad electrically connected to the second semiconductor chip stack through a second bonding wire (82), and a connecting pad electrically connected to the controller, and
the controller is electrically connected to the substrate through a solder ball (70) connected to the connecting pad.
Regarding claim 9, figure 1 of Hasegawa discloses a substrate (10) extending in a first direction and a second direction intersecting the first direction;
a first spacer (lowermost 20) disposed on the substrate;
a first semiconductor chip stack (20) disposed on the first spacer, the first semiconductor chip stack includes a plurality of first semiconductor chips stacked in a third direction intersecting the first direction and the second direction;
a second spacer (lowermost 30) disposed on the substrate, the second spacer is spaced apart from the first spacer in the first direction;
a second semiconductor chip stack (30) disposed on the second spacer, the second semiconductor chip stack includes a plurality of second semiconductor chips stacked in the third direction; and
a mold layer (91) integrally covering the first semiconductor chip stack and the second semiconductor chip stack, the mold layer is in direct contact with side surfaces of the first spacer and side surfaces of the second spacer,
wherein the first semiconductor chip stack and the second semiconductor chip stack do not overlap each other in the third direction, and
a width of the first spacer in the first direction is greater than a width of the second spacer in the first direction.
Regarding claim 10, figure 1 of Hasegawa discloses the first semiconductor chip stack comprises a first semiconductor chip (20) disposed on an upper side of the first spacer, and a second semiconductor chip disposed on the first semiconductor chip;
the second semiconductor chip stack comprises a third semiconductor chip (30) disposed on an upper side of the second spacer, and a fourth semiconductor chip disposed on the third semiconductor chip; and
thicknesses of the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip are equal to each other in the third direction.
Regarding claim 12, figure 1 of Hasegawa discloses the first spacer is disposed between the first semiconductor chip and the substrate (10); and
the second spacer is disposed between the third semiconductor chip and the substrate.
Regarding claim 13, figure 1 of Hasegawa discloses a distance between the first semiconductor chip and the third semiconductor chip is greater than a distance between the second semiconductor chip and the fourth semiconductor chip.
Regarding claim 14, figure 1 of Hasegawa discloses the second semiconductor chip and the fourth semiconductor chip do not overlap each other in the third direction.
Regarding claim 15, figure 1 of Hasegawa discloses a controller (40) disposed between the first spacer (20) and the second spacer (30) and disposed on the substrate (10).
Regarding claim 16, figure 1 of Hasegawa discloses the substrate (10) comprises a wiring structure (¶ 47-48) including a first passivation layer and a second passivation layer spaced apart from each other in the third direction, a first wiring layer in the first passivation layer, and a second wiring layer in the second passivation layer;
the first wiring layer comprises a first upper pad and a second upper pad electrically connected to the first semiconductor chip stack through a first bonding wire (81), a third upper pad and a fourth upper pad electrically connected to the second semiconductor chip stack through a second bonding wire (82), and a connecting pad electrically connected to the controller (40); and
the controller is electrically connected to the substrate through a solder ball (70) connected to the connecting pad.
Claims 9-11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated Shen et al. (US PG Pub 2023/0246000, hereinafter Shen).
Regarding claim 9, figure 1 of Shen discloses a substrate (104) extending in a first direction and a second direction intersecting the first direction;
a first spacer (110a) disposed on the substrate;
a first semiconductor chip stack (108a-d) disposed on the first spacer, the first semiconductor chip stack includes a plurality of first semiconductor chips stacked in a third direction intersecting the first direction and the second direction;
a second spacer (110b) disposed on the substrate, the second spacer is spaced apart from the first spacer in the first direction;
a second semiconductor chip stack (108m-p) disposed on the second spacer, the second semiconductor chip stack includes a plurality of second semiconductor chips stacked in the third direction; and
a mold layer (102) integrally covering the first semiconductor chip stack and the second semiconductor chip stack, the mold layer is in direct contact with side surfaces of the first spacer and side surfaces of the second spacer,
wherein the first semiconductor chip stack and the second semiconductor chip stack do not overlap each other in the third direction, and
a width of the first spacer in the first direction (diagonal to the sidewall of the spacer) is greater than a width (measured along a narrower portion) of the second spacer in the first direction.
Regarding claim 10, figure 1 of Shen discloses the first semiconductor chip stack comprises a first semiconductor chip (108a) disposed on an upper side of the first spacer, and a second semiconductor chip (108b) disposed on the first semiconductor chip;
the second semiconductor chip stack comprises a third semiconductor chip (108m) disposed on an upper side of the second spacer, and a fourth semiconductor chip (108n) disposed on the third semiconductor chip; and
thicknesses of the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip are equal to each other in the third direction.
Regarding claim 11, figure 1 of Shen discloses an outer wall of the first semiconductor chip (108a) and an outer wall of the first spacer (110a) are aligned with each other;
an inner wall of the first semiconductor chip and an inner wall of the first spacer are not aligned with each other;
an outer wall of the third semiconductor chip (108n) and the outer wall of the second spacer (110b) are aligned with each other;
an inner wall of the third semiconductor chip and the inner wall of the second spacer are not aligned with each other; and
a distance in the first direction between the outer wall of the first semiconductor chip and the outer wall of the third semiconductor chip is greater than a distance in the first direction between the inner wall of the first semiconductor chip and the inner wall of the third semiconductor chip.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa.
Regarding claim 17, figure 1 of Hasegawa discloses a semiconductor package comprising:
a substrate (10) extending in a first direction and a second direction intersecting the first direction;
a first spacer (lowermost 20) disposed on the substrate;
a first semiconductor chip stack (20) disposed on the first spacer, the first semiconductor chip includes a plurality of first semiconductor chips stacked in a third direction intersecting the first direction and the second direction;
a second spacer (lowermost 30) disposed on the substrate, the second spacer is spaced apart from the first spacer in the first direction;
a second semiconductor chip stack (30) disposed on the second spacer, the second semiconductor chip includes a plurality of second semiconductor chips stacked in the third direction;
a mold layer (91) integrally covering the first semiconductor chip stack and the second semiconductor chip stack, the mold layer is in direct contact with side surfaces of the first spacer and side surfaces of the second spacer; and
a controller (40) disposed between the first spacer and the second spacer and disposed on the substrate,
wherein the first spacer comprises a first layer (20), and a first bonding layer (21) disposed between the first silicon layer and the substrate,
the second spacer includes a second layer (30), and a second bonding layer (31) disposed between the second silicon layer and the substrate, and
a width of the first spacer in the first direction is greater than a width of the second spacer in the first direction.
Hasegawa does not explicitly disclose the first and second spacers include a silicon layer.
However, it would have been obvious to for the spacers to include a silicon layer since silicon is a well known material in the art for semiconductor chips.
Regarding claim 18, figure 1 of Hasegawa discloses a height of an upper side of the first bonding layer (21) and a height of an upper side of the second bonding layer (31) are equal to each other with respect to an upper side of the substrate (10).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU-HSI DAVID SUN whose telephone number is (571)270-5773. The examiner can normally be reached Mon-Fri 8am-4pm ET.
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/YU-HSI D SUN/ Primary Examiner, Art Unit 2817
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