Prosecution Insights
Last updated: July 17, 2026
Application No. 18/660,322

STRUCTURE OF HIGH-RESISTIVITY SILICON-ON-INSULATOR EMBEDDED WITH CHARGE CAPTURE LAYER AND MANUFACTURE THEREOF

Non-Final OA §112
Filed
May 10, 2024
Priority
May 19, 2023 — CN 202310573286.1
Examiner
CHI, SUBERR L
Art Unit
Tech Center
Assignee
Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
547 granted / 649 resolved
+24.3% vs TC avg
Minimal +3% lift
Without
With
+2.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
28 currently pending
Career history
669
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
69.2%
+29.2% vs TC avg
§102
15.2%
-24.8% vs TC avg
§112
11.9%
-28.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 649 resolved cases

Office Action

§112
DETAILED ACTION Notice of AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . IDS The IDS document(s) filed on May 10, 2024 has been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action. Claim Objection As to claim 9, the Examiner suggests “by a chemical vapor deposition”. Claim Rejections – 35 U.S.C. § 112(b) The following is a quotation of 35 U.S.C. § 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1-10 are rejected under 35 U.S.C. § 112(b) or pre-AIA 35 U.S.C. § 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant, regards as the invention. As to claim 1, it is unclear if a roughness treatment is actually performed because the limitation “to be subjected to a roughness treatment” (emphasis added) is incomplete for omitting essential steps, such omission amounting to a gap between the steps. See MPEP § 2172.01. Here, the phrasing “to be subjected to a roughness treatment” merely expresses an intent to perform a future step of a roughness treatment but does not recite a present roughness treatment step. Contrast with the claim construction of claims 7-8 which recites “subjected to a surface treatment” and is a present, actual process step. As to claims 2-6, it is unclear if the recited process steps are actually performed because they all claim dependence from “to be subjected to a roughness treatment” of parent claim 1. No Prior Art Applied The Examiner was unable to find prior art applicable to the claims as presently written. Wang et al. (U.S. Patent Publication No. 2018/0233400 A1), as cited in the IDS and hereafter “Wang”, is the closest prior art reference. Wang teaches in FIG. 3 providing a first substrate 44. Although one might be inclined to call the handle substrate 42 the first substrate, the handle substrate 42 is not subjected to a roughness treatment to form an uneven morphology because it is the semiconductor oxide layer 44 that is instead subject to a roughness treatment, e.g. cleaning step. See Wang, ¶ [0038]. If Wang is used to teach forming a surface treatment layer 46, wherein the surface treatment layer has an uneven surface morphology, then Wang does not teach forming a polysilicon layer on the surface treatment layer because layer 48 is buried oxide and layer 50 is a single crystal silicon layer. Further, Wang does not teach the surface treatment layer 46 as having an uneven surface morphology nor does it inherently have an uneven surface morphology simply because it is formed on top of the first substrate 44 with an uneven morphology. Prior Art Not Relied Upon The following prior art was not relied upon but is made of record: Lottes et al. (U.S. Patent Publication No. 2024/0258155 A1) Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUBERR CHI whose telephone number is (571)270-3955. The examiner can normally be reached 10am to 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SUBERR L CHI/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

May 10, 2024
Application Filed
Jun 03, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12685150
EXTENDED VIA CONNECT FOR PIXEL ARRAY
3y 6m to grant Granted Jul 14, 2026
Patent 12672380
PHOTODIODE WITH ORTHOGONAL LAYER STRUCTURE
2y 11m to grant Granted Jun 30, 2026
Patent 12666659
SEMICONDUCTOR MEMORY STRUCTURE HAVING DRAIN STRESSOR, SOURCE STRESSOR AND BURIED GATE AND METHOD OF MANUFACTURING THE SAME
2y 11m to grant Granted Jun 23, 2026
Patent 12666884
SiC SEMICONDUCTOR SUBSTRATE AND FABRICATION METHOD OF THE SiC SEMICONDUCTOR SUBSTRATE
3y 0m to grant Granted Jun 23, 2026
Patent 12660416
LIGHT-TRANSMITTING DISPLAY PANEL, DISPLAY PANEL AND DISPLAY APPARATUS
4y 4m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
87%
With Interview (+2.8%)
2y 9m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 649 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month