DETAILED ACTION
Election/Restrictions
A restriction requirement was mailed on 6/16/26.
Applicant's election with traverse of species A in the reply filed on 6/22/26 is acknowledged. The traversal is on the ground(s) that there is no serious burden (remarks, 6/22/26, page 12-13). This is not found persuasive because the serious burden was described in paragraphs 2-4 of the restriction requirement, and include separate searches (section 4) to find the different distinguishing features, listed in the table (section 2).
The requirement is still deemed proper and is therefore made FINAL.
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/10/24 is in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the information disclosure statement has been considered by the examiner.
The information disclosure statement (IDS) submitted on 1/2/25 is in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the information disclosure statement has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), first paragraph:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Summary of the claims and the issues
Claims 1, 17, and 20 recite, in part:
(claim 1)
… wherein the gate electrode includes a lower surface facing a bottom surface of the first trench, an upper surface opposite to the lower surface, and n number of side surfaces connecting the lower surface and the upper surface,
wherein an angle of the m-th side surface of the gate electrode with respect to the lower surface of the gate electrode is different from an angle of the (m-1)-th side surface of the gate electrode with respect to the lower surface of the gate electrode,
wherein n is a natural number greater than 2, and
wherein m is equal to or smaller than n.
(claim 17)
… wherein the second conductivity type doped well region includes an inner bottom surface facing the bottom surface of the second trench, and k number of side surfaces extending from the inner bottom surface, and
wherein an angle of the j-th side surface of the second conductivity type doped well region with respect to the inner bottom surface of the second conductivity type doped well region is different from an angle of the (j-1)-th side surface of the second conductivity type doped well region with respect to the inner bottom surface of the second conductivity type doped well region,
wherein k is a natural number greater than 2, and
wherein j is equal to or smaller than k.
(claim 20)
…wherein the first trench includes a bottom surface, and n number of side walls extending from the bottom surface of the first trench, and
wherein angles of the n number of side walls of the first trench with respect to the bottom surface gradually increase from the n-th side wall extending from the bottom surface of the first trench to the first side wall positioned at the top of the first trench,
wherein the second trench includes a bottom surface, and k number of side walls extending from the bottom surface of the second trench, and
wherein angles of the k number of side walls of the second trench with respect to the bottom surface gradually increase from the k-th side wall extending from the bottom surface of the second trench to the first side wall positioned at the top of the second trench.
In summary, the claims require, in part:
(I) a specific shape of a gate electrode (claim 1),
(II) a specific shape of a second conductivity type doped well region (claim 17), and
(III) specific shapes of a first trench and a second trench (claim 20).
Regarding (I) and (III), the shape of the gate electrode results directly by being formed within the first trench of claim 20.
Regarding (II) and (III), the shape of the second conductivity type doped well region results directly by being formed within the second trench of claim 20.
Regarding (I), (II), and (III), the disclosed method of forming the first trench (see Figs. 16-18) is analogous to the method of forming the second trench (see Figs. 11-13). Specifically:
Elements 500, 510, 521, h11, Ɵ11, and 4th etch in Fig. 16 correspond with 600, 610, 621, h21, Ɵ21, and 1st etch in Fig. 11, respectively.
Elements 500, 510, 521, 522, h11, h12, Ɵ11, Ɵ12, and 5th etch in Fig. 17 correspond with 600, 610, 621, 622, h21, h22, Ɵ21, Ɵ22 and 2nd etch in Fig. 12, respectively.
Elements 500, 510, 521, 522, 523, h11, h12, h13, Ɵ11, Ɵ12, Ɵ13, and 6th etch in Fig. 18 correspond with 600, 610, 621, 622, 623, h21, h22, h23, Ɵ21, Ɵ22, Ɵ23, and 3rd etch in Fig. 13, respectively.
Thus, the issues in all of the claims boil down to issues with forming a trench. To make the discussion easier, only the “first trench” 500 of Fig. 18, referring to claim 20, within which the gate electrode of claim 1 will be formed, will be specifically discussed in this rejection. However, as explained above, all claims suffer from lack of adequate written description for analogous reasons, using the above-noted equivalency between the processes of Figs. 16-18 and of Figs. 11-13.
Explanation of the rejection
In determining that the claims do not satisfy the written description requirement, the Office has considered the factors as specific in MPEP 2163, including the following:
Actual reduction to practice
Disclosure of drawings or structural chemical formulas
Method of making the claimed invention
Level of skill and knowledge in the art
Predictability in the art
The specification does not show actual reduction to practice for claims 1, 17, or 20, or any claim dependent therefrom [factor A].
The application shows in figures [factors A and B] a device in Fig. 21, shows a process for forming the device in Figs. 10-21 [factors A, B, and C], and describes the drawings in associated specification text. However, the drawings are highly generic and do not describe any specific working example.
For example, regarding the shape of the gate electrode or the first trench, Fig. 16 generically shows the results of a “fourth etch”, forming bottom surface 510 and a first side wall 521; Fig. 17 generically shows the results of a “fifth etch”, forming a modified bottom surface 510 (that is still horizontal, but is deeper within 131 than in Fig. 16), shows the first side wall 521 being unmodified, and showing a new side wall 522; and Fig. 18 generically shows the results of a “sixth etch”, forming a yet-again modified bottom surface 510 (that is still horizontal, but is deeper within 131 than in Fig. 16 or Fig. 17), showing the first side wall 521 being unmodified, showing the second side wall 522 being unmodified, and showing a new third side wall 523. However, the drawings alone do not describe specifically how the claimed shapes of the trench arises. In other words, the drawings do not show how/why the trench’s straight bottom surface and straight first, second, and third side walls are formed having the specific geometry with angles Ɵ11, Ɵ12, and Ɵ13 and with the heights h11, h12, and h13. The drawings merely show “4th etch”, “5th etch”, and “6th etch”, but do not disclose any features of these etches (e.g. etchant type, etchant material, etching process parameters) that result in the specific geometry.
Regarding factors A, B, and C, while the drawings alone do not show an actual reduction to practice, similarly, the combination of text and figures does not show an actual reduction to practice.
The text of the specification only discloses that layer 131 may be made from SiC, and discloses only one example thereof (“4H SiC”) (see para 30-31). No other specific materials are disclosed. Rather, the specification makes an all-encompassing statement suggesting any other material may be used (“the material [and other properties]… of the first conductivity type epitaxial layer 131 are not limited thereto, and may be variously changed”) (see para 31).
However, neither the text or drawings describe:
(a) what specific etching type(s) is/are used (e.g. physical etching, chemical etching, plasma etching, etc.) for the 4th, 5th, and 6th etches,
(b) what specific etchant(s)s is/are used (e.g. CF4, SF6, CHF3, NaOH, H3PO4, KOH, KNO3, etc.) for the 4th, 5th, and 6th etches, or
(c) what specific etching conditions are provided (e.g. wattage of plasma used in plasma etching; frequency used to supply plasma; flow rate of gases; pressures of gases; concentrations of wet chemicals; etc.) during the 4th, 5th, and 6th etches.
Regarding factors D and E, the specification shows results of etches which one of ordinary skill in the art would find it very difficult to understand, without providing any details about the etches. For example, Fig. 16 shows an etch that etches the material 131 uniformly vertically so that the surface 510 is recessed. This is not difficult to understand because the etch acts uniformly on the single material 131 everywhere the etch is applied to 131. However, Fig. 17 shows that the 5th etch both recesses the bottom surface 510 to a lower level within 131, but also simultaneously creates a slanted wall 522 at an angle Ɵ12. One of ordinary skill in the art would not understand what etchants to use and what etching conditions to apply so that the same etching step applied to an entire trench 500 would recess the material 131 in the middle of 500 and simultaneously etch 131 along an angle Ɵ12 near the side surface of 500. Furthermore, Fig. 18 shows that the 6th etch does three things to a single material 131: recesses the bottom surface 510 to its position at the bottom of h13, does not affect the side of 521 at all, and etches the material 131 at an angle Ɵ13 only where 510 is not etched near the middle of 500 and not where 522 already exists. One of ordinary skill in the art would not understand what etchants to use and what etching conditions to apply so that the same etch causes three different effects to a single material.
Furthermore, the claims are very broad and cover any semiconductor material (e.g. Si, Ge, diamond, Te, BN, BP, Bas, SiGe, SiC, AlN, AlP, AlAs, GaN, AlGaN, GaSb, InN, InSb, CdSe, CdTe, ZnO, ZnS, ZnTe, PbSe, Cu2S, CuCl, SNS, Bi2Te3, Cd3P2, Zn3As2, TiO2, SnO2, SrTiO3, BaTiO3, VO2, LaCaMnO3, TlBr, FeS2, CuZnSnS4, PbSnTe, AlAsSb, HgCdTe, etc.) patterned to have the n side walls therein. However, the specification only discloses that this layer may be made from SiC, with only one example thereof (“4H SiC”) (see para 30-31).
The claims cover creating n>2 side surfaces at angles Ɵ1n, without any limit on n (n could be 3, 5, 10, 15, etc.). The claims cover forming these n side surfaces in any semiconductor material. The specification has not adequately described how to even form 3 side surfaces in SiC, much less how to form any number of side surfaces (greater than 3) in any semiconductor material.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
The entirety of the discussion in the rejection above, for written description, is relied upon for this enablement rejection, but is not repeated, for the sake of brevity.
The determination of the propriety of a rejection based upon the scope of a claim relative to the scope of enablement involves “determin[ing] if one skilled in the art is enabled to make and use the entire scope of the claimed invention without undue experimentation.” See MPEP 2164.08. Determination if undue experimentation is necessary is made based on the “In re Wands” factors, “considering all of the evidence related to each of these factors, and any conclusion of nonenablement must be based on the evidence as a whole.” See MPEP 2164.01(a). The Wands factors, listed next, have been considered in the decision of non-enablement. (A) The breadth of the claims; (B) The nature of the invention; (C) The state of the prior art; (D) The level of one of ordinary skill; (E) The level of predictability in the art; (F) The amount of direction provided by the inventor; (G) The existence of working examples; and (H) The quantity of experimentation needed to make or use the invention based on the content of the disclosure. In re Wands, 858 F.2d 731, 737, 8 USPQ2d 1400, 1404 (Fed. Cir. 1988), However, “it is not necessary to discuss each factor in the written enablement rejection. The language should focus on those factors, reasons, and evidence that lead the examiner to conclude that the specification fails to teach how to make and use the claimed invention without undue experimentation or that the scope of any claimed enablement provided to one skilled in the art is not commensurate with the scope of protection sought by the claims.” See MPEP 2164.04.
Regarding (A), as described above, the breadth of the claims is gigantic, because the claims cover n>2 side surfaces and/or or k>2 side surfaces (with no limit on how high n or k may be) at different angles in any semiconductor material.
Regarding (B)-(E), the nature of the invention is complex, compared to that of the prior art and level of skill of one in the prior art, because the claim covers forming n side surfaces in any material wherein, for most side surfaces, a single etching step has many different effects on a single target material. This is generally not known in the prior art, and no guidance has been provided by the Applicant how to accomplish this in any specific material, much less to accomplish this in any semiconductor material.
Regarding (F) and (G), the rejection above discusses how little direction was provided by the Applicant, and that no working example was disclosed (only a single example material was disclosed; no specific etchants or etching parameters were disclosed).
Regarding (H), undue experimentation would be required to accomplish this claimed invention for any single material. For any one semiconductor material (e.g. Si, Ge, diamond, Te, BN, BP, Bas, SiGe, SiC, AlN, AlP, AlAs, GaN, AlGaN, GaSb, InN, InSb, CdSe, CdTe, ZnO, ZnS, ZnTe, PbSe, Cu2S, CuCl, SNS, Bi2Te3, Cd3P2, Zn3As2, TiO2, SnO2, SrTiO3, BaTiO3, VO2, LaCaMnO3, TlBr, FeS2, CuZnSnS4, PbSnTe, AlAsSb, HgCdTe, etc.), choose any single etchant (e.g. CF4, SF6, CHF3, NaOH, H3PO4, KOH, KNO3, etc.) for the 1st and/or 4th etch, choose any other etchant for the 2nd and/or 5th etch, choose any other etchant for the 3rd and/or 6th etch, and choose such etchants up to all values for n and/or k. Then, choose any process parameters (e.g. wattage of plasma used in plasma etching; frequency used to supply plasma; flow rate of gases; pressures of gases; concentrations of wet chemicals; etc.) for each etchant. Then, vary amongst all values of the possible process parameters. Then, vary amongst all possible combinations of etchants. The number of combinations needing to be explored is almost infinite.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 6, 9, 13, 16, 18-19, and 20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant) regards as the invention.
Claims 6, 9, 13, 16, 18, and 20 recite the limitation “…gradually increase…” The metes and bounds of the claimed limitation can not be determined for the following reasons:
The term "gradually" is a relative term that renders the claim indefinite. It is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “gradually” describes a target a difference between two angles and implicitly requires some value of this difference beyond which one is not “gradual”. Neither the claims, nor the specification, defines this boundary. It is unclear which of the following values would be “gradual” and which would not: differences of 1 degree, 3 degrees, 5 degrees, 10 degrees, 15 degrees, 20 degrees, 25 degrees, 30 degrees, 40 degrees, 50 degrees, etc. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and the claim is unclear.
Claim 19 depends from claim 18 and inherits its deficiencies.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102, some of which form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 7, and 10 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2016/0276450 A1 (“Kobayashi”).
Kobayashi teaches, for example:
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Kobayashi teaches:
1. A semiconductor device comprising:
a substrate (10a, see e.g. Fig. 4B) having a first conductivity type (n-type);
a first conductivity type epitaxial layer (12a, see e.g. Fig. 4B) on a first surface (top surface) of the substrate, the first conductivity type epitaxial layer defining a first trench (Tr2, see e.g. Fig. 4B);
a gate electrode (24a, see e.g. Fig. 6B) inside the first trench;
a gate insulating layer (26a, see e.g. Fig. 6B) insulating the first conductivity type epitaxial layer from the gate electrode;
a source electrode (32, see e.g. Fig. 8A) on the first conductivity type epitaxial layer;
second conductivity type doped well regions (22, see e.g. Fig. 8A) and first conductivity type doped layers between the first conductivity type epitaxial layer and the source electrode; and
a drain electrode (30, see e.g. Fig. 9) on a second surface (bottom) of the substrate,
wherein the gate electrode (24) includes (see e.g. Fig. 2)
a lower surface (bottom of 24, where T1 is labeled in Fig. 2) facing a bottom surface of the first trench,
an upper surface (top of 24) opposite to the lower surface, and
n number of side surfaces (sides of 24, e.g. where T2, T3, and T4 are labeled) connecting the lower surface and the upper surface,
wherein an angle of the m-th side surface of the gate electrode with respect to the lower surface of the gate electrode is different from an angle of the (m-1)-th side surface of the gate electrode with respect to the lower surface of the gate electrode (see Fig. 2),
wherein n is a natural number greater than 2 (see three side surfaces identified above), and
wherein m is equal to or smaller than n (the angle of the first side surface at T2 is different than that of the second side surface at T3, and the angle of the side surface at T3 is different than the angle of the side surface at T4).
2. The semiconductor device of claim 1, wherein the m-th side surface of the gate electrode is closer to the lower surface of the gate electrode than the (m-1)-th side surface of the gate electrode is to the lower surface of the gate electrode, and the angle of the (m-1)-th side surface of the gate electrode with respect to the lower surface of the gate electrode is larger than the angle of the m-th side surface of the gate electrode with respect to the lower surface of the gate electrode (see Fig. 2, wherein the angle of the first side surface at T2 is smaller than the angle of the second side surface at T3).
3. The semiconductor device of claim 1, wherein the n number of side surfaces of the gate electrode include: a first side surface extending down from the upper surface of the gate electrode; and a second side surface extending down from the first side surface, and wherein an angle of the first side surface of the gate electrode with respect to the lower surface of the gate electrode is larger than an angle of the second side surface of the gate electrode with respect to the lower surface of the gate electrode (see Fig. 2, wherein the angle of the second side surface at T3 is larger than the angle of the first side surface at T2; T3 “extends down from the upper surface” from the top of the second surface to the bottom of the second surface).
7. The semiconductor device of claim 1, wherein the first trench includes: a bottom surface; and n number of side walls extending from the bottom surface, and an angle of the m-th side wall of the first trench with respect to the bottom surface of the first trench is different from an angle of the (m-1)-th side wall of the first trench with respect to the bottom surface of the first trench (see discussion of claim 1).
10. The semiconductor device of claim 1, wherein the first conductivity type epitaxial layer further includes a second trench spaced apart from the first trench, and the second conductivity type doped well regions are inside the second trench (see e.g. Fig. 1, wherein the leftmost gate 24 is spaced from the rightmost region 22, the rightmost region 22 being in a trench within S).
Conclusion
Conclusion / Prior Art
The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited.
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896
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