DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/20/2026 has been entered.
Response to Amendment
Amendment dated 01/20/2026 has been acknowledged. Claims 1, 16, 24, 33, 41 were amended. Claims 19-23, 26-29 were previously cancelled. Claims 1-18, 24-25, 30-47 remain pending in the application.
Response to Arguments
Applicant’s arguments filed 01/102026 has been acknowledged but are moot since a new ground of rejection are made in view new references HORII (US 2015/0380247 A1) and Ryu et al. (US 2006/0255423 A1) and Siemieniec reference no longer used in current rejection and none of the arguments applies to combination of references used (see rejection below). Applicant’s argument overcomes rejection under 35 USC § 112. Accordingly, associated 112(b) rejections of claims 33-34 are hereby withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically teaches d as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 16 & 30 are rejected under 35 U.S.C. 103 as being unpatentable over HORII (US 20150380247 A1) in view of Ryu et al. (US 2006/0255423 A1)
Regarding claim 1, HORII teaches,
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A method of fabricating a power semiconductor device (Fig. 1), the method comprising:
providing a semiconductor layer structure (10, para [0039]) comprising:
a semiconductor drift region (13, para [0039]) of a first conductivity type, the semiconductor layer structure comprising an active region (region under gate 40 as marked) ;
and forming a plurality of guard rings (6, para [0064]) of a second conductivity type in the semiconductor layer structure to form an edge termination region,
…… and providing a source contact (60, para [0039]) on the active region, wherein the guard rings are laterally spaced apart from the source contact (Fig. 1).
But HORII does not explicitly teach,
wherein forming the guard rings comprises sequentially performing first and second ion implantation processes using first and second mask patterns on the semiconductor layer structure, respectively
But Ryu et al. teaches,
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forming the guard rings (including 316 & 317) comprises sequentially performing first (first implant to form 317, para [0075]) and second ion implantation processes (second implant to form 317, para [0075]) ) using first (mask pattern 500 used while first implant to form 316, para [0075]) and second mask patterns on the semiconductor layer (mask pattern 500 used while second implant to form 316, para [0075]).
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention, to modify HORRII such that the method further comprises: forming the guard rings (6/316 & 317) comprises sequentially performing first and second ion implantation processes using first and second mask patterns on the semiconductor layer, according to teaching of Ryu, in order to form guard rings 6 as junction barrier grid (Ryu, para [0075]) for the purpose of forming a junction barrier Schottky diode (JBS diode), as taught by Ryu (para [0031]).
Regarding claim 16, HORII teaches,
A method of fabricating a power semiconductor device (FIG. 1), the method comprising:
providing a semiconductor layer structure (10, para [0039]) comprising a semiconductor drift region (13, para [0039]) of a first conductivity type, the semiconductor layer structure comprising an active region (region under gate 40 as marked above);
and forming a plurality of guard rings (6, para [0064]) of a second conductivity type in the semiconductor layer structure to form an edge termination region,
wherein the guard rings are electrically floating (as seen in FIG. 1, guard rings are isolated from source electrode 60 by gate insulating film 20 and interlayer insulating film 40 and hence electrically floating),
But HORII does not explicitly teach,
wherein forming the guard rings comprises performing first and second ion implantation processes to form first and second portions of the guard rings extending in the semiconductor layer structure to first and second depths respectively, wherein the second ion implantation processes comprises a greater implantation energy than the first ion implantation process.
But Ryu et al. teaches,
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wherein forming the guard rings (including 316 & 317) comprises performing first (first implant to form 317, para [0075]and second ion implantation processes (second implant to form 316, para [0075]) to form first (317) and second portions (316) of the guard rings extending in the semiconductor layer structure to first and second depths respectively (depth of 317 and 316 from first main surface 10a, para [0040] respectively), wherein the second ion implantation processes comprises a greater implantation energy than the first ion implantation process (see para [0075], implant energy to form 317 is less than the implant energy to form 316 i.e. implant energy to form 316 is higher than the implant energy to form 317)
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention, to modify HORRII such that the method further comprises: wherein forming the guard rings comprises performing first and second ion implantation processes to form first and second portions of the guard rings extending in the semiconductor layer structure to first and second depths respectively, wherein the second ion implantation processes comprises a greater implantation energy than the first ion implantation process, according to teaching of Ryu, in order to form guard rings 6 as junction barrier grid (Rye, para [0075]) for the purpose of forming a junction barrier Schottky diode (JBS diode), as taught by Ryu (para [0031]).
Regarding claim 30, HORII & Ryu teach the method of claim 1 and further teaches, the edge termination region (guard rings 6) is adjacent a periphery of the active region (Fig. 1 above).
Allowable Subject Matter
Claims 2-15, 17-18, 31-35, 40 & 45-47 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
With respect to claims 2 & 17 the prior art of record does not appear to teaches , suggest, or provide motivation for combination to following limitation:
wherein the first mask pattern comprises openings of a different width than the second mask pattern (claim 2).
wherein performing first and second ion implantation processes comprises sequentially forming first and second mask patterns on the semiconductor layer structure, respectively (claim 17).
Claims 3-15, 40, 45 are objected to being dependent on claim 2.
Claim 18, 31-35, 46-47 are objected to being dependent on claim 16.
Claims 24-25, 36-39, 41-44 are allowed.
With respect to claim 24, the prior art made of record does not teach or suggest either alone or in combination “wherein a first lateral spacing between the first portions is different than a second lateral spacing between the second portions” in further combination with the additionally claimed limitations, as they are claimed by the Applicant.
Regarding claim 24, HORII teaches,
A method of fabricating a power semiconductor device (Fig. 1), the method comprising:
providing a semiconductor layer structure (10, para [0039]) comprising a semiconductor drift region (13, para [0039]) of a first conductivity type,
the semiconductor layer structure comprising an active region (region under gate 40 as marked);
and forming a plurality of guard rings (6, para [0064]) of a second conductivity type in the semiconductor layer structure to form an edge termination region,
wherein the guard rings are electrically floating (as seen in FIG. 1, guard rings are isolated from source electrode 60 by gate insulating film 20 and interlayer insulating film 40 and hence electrically floating).
But HORII does not explicitly teach,
wherein forming the guard rings comprises performing first and second ion implantation processes to form first and second portions of the guard rings extending in the semiconductor layer structure to first and second depths, respectively,
wherein a first lateral spacing between the first portions is different than a second lateral spacing between the second portions.
But Ryu teaches,
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forming the guard rings (including 316 & 317) comprises performing first (first implant to form 317, para [0075]and second ion implantation processes (second implant to form 316, para [0075]) to form first (317) and second portions (316) of the guard rings extending in the semiconductor layer structure to first and second depths respectively (depth of 317 and 316 from first main surface 10a, para [0040] respectively)
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention, to modify HORRII such that the method further comprises: wherein forming the guard rings comprises performing first and second ion implantation processes to form first and second portions of the guard rings extending in the semiconductor layer structure to first and second depths respectively, according to teaching of Ryu, in order to form guard rings 6 as junction barrier grid (Rye, para [0075]) for the purpose of forming a junction barrier Schottky diode (JBS diode), as taught by Ryu (para [0031]).
But HORII & Ryu still fails to teach,
,wherein a first lateral spacing between the first portions is different than a second lateral spacing between the second portions.
The other cited arts, either alone or in combination, fails to cure deficiencies of HORII & Ryu.
Claims 25, 36-39 are allowed being dependent on claim 24.
With respect to claim 41, the prior art made of record does not teach or suggest either alone or in combination “performing a second ion implantation process using the second mask pattern on the semiconductor layer structure to form………..at least one shielding pattern in the active region; forming at least one gate trench in the active region, wherein the at least one shielding pattern is under the at least one gate trench” in further combination with the additionally claimed limitations, as they are claimed by the Applicant.
Regarding claim 41, HORII teaches,
A method of fabricating a power semiconductor device (FIG. 1), the method comprising:
providing a semiconductor layer structure (10, para [0039]) of a first conductivity type, the semiconductor layer structure comprising an active region (region under gate 40 as marked) and an edge termination region (comprising guard rings 6, para [0064]) adjacent the active region;
…….and providing a source contact (60, para [0039]) on the active region, wherein the guard rings are laterally spaced apart from the source contact (Fig. 1)
But HORII does not explicitly teach,
performing a first ion implantation process using a first mask pattern on the semiconductor layer structure to form first portions of guard rings of a second conductivity type in the edge termination region;
performing a second ion implantation process using a second mask pattern on the semiconductor layer structure to form second portions of the guard rings in the edge termination region and at least one shielding pattern in the active region ;
and forming at least one gate trench in the active region, wherein the at least one shielding pattern is under the at least one gate trench;
Meanwhile, Ryu teaches,
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performing a first ion implantation process (first implant to form 317, para [0075]) using a first mask pattern (mask pattern 500 used while first implant to form 317, para [0075]) on the semiconductor layer structure to form first portions of guard rings (317) of a second conductivity type in the edge termination region;
performing a second ion implantation process (second implant to form 316, para [0075] using a second mask pattern (mask pattern 500 used while first implant to form 316, para [0075]) on the semiconductor layer structure to form second portions of the guard rings (316) in the edge termination region …….
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention, to modify HORRII such that the method further comprises: performing a first ion implantation process using a first mask pattern on the semiconductor layer structure to form first portions of guard rings of a second conductivity type in the edge termination region; performing a second ion implantation process using a second mask pattern on the semiconductor layer structure to form second portions of the guard rings in the edge termination region, according to teaching of Ryu, in order to form guard rings 6 as junction barrier grid (Rye, para [0075]) for the purpose of forming a junction barrier Schottky diode (JBS diode), as taught by Ryu (para [0031]).
HORII & Ryu still does not explicitly teach,
performing a second ion implantation process using the second mask pattern on the semiconductor layer structure to form at least one shielding pattern in the active region
and forming at least one gate trench in the active region, wherein the at least one shielding pattern is under the at least one gate trench;
The other cited arts, either alone or in combination, fails to cure deficiencies of HORII & Ryu.
Claims 42-44 are allowed being dependent on claim 41.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final ac I have tion. (FP 7.40)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHATIB A RAHMAN whose telephone number is (571)270-0494. The examiner can normally be reached on MON-FRI 8:00 am- 5:00 pm (Arizona).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Steven Gauthier, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.A.R/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813