DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d).
Information Disclosure Statement
The information disclosure statement filed on 05/10/2024 has been acknowledged and a signed copy of the PTO-1449 is attached herein.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 15 recites “a at least one support layer between the first electrode structures” grammatically incorrect.
Claim 20 recites “an upper interlayer insulating layer on the lower interlayer insulating layer and the plate layer,” and thereafter recites “wherein an upper surface of the plate layer is in direct contact with an upper interlayer insulating layer.” The use of indefinite article in the second instance renders it unclear whether the Applicant intends the previously recited upper interlayer insulating layer or an additional, distinct layer. Examiner suggests “wherein an upper surface of the plate layer is in direct contact with the upper interlayer insulating layer.”
Claims 16-19 are rejected by virtue of their dependence on already rejected base claim 15.
Claim Rejections - 35 USC § 102
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3-8 are rejected under 35 U.S.C. 102(A)(1) as being anticipated by Lee et al. (US 2023/0030176 A1, hereinafter “Lee’).
In regards to claim 1, Lee discloses (See, for example, Figs. 2) a semiconductor device, comprising:
a lower structure (see for example, 120, 130, 132) including a conductive region (see, for example, 120a, 120b, 120c, 130, 132);
a capacitor (220, 230, 232) electrically connected to the conductive region of the lower structure,
wherein the capacitor includes first electrode structures (220),
at least one support layer (See, for example, 208a, 204a) between the first electrode structures (220),
a dielectric layer (230) covering the first electrode structures (220) and the at least one support layer (208a, 204a), and
a second electrode structure (232) on the dielectric layer (230);
a plate layer (234) covering the capacitor;
a polishing stop layer (242/242a) covering a side surface of the plate layer (234/240a);
a lower interlayer insulating layer (246/246a) covering the polishing stop layer (242/242a); and
an upper interlayer insulating layer (252a/254) on the lower interlayer insulating layer (246a/246) and the plate layer (234/240a),
wherein the plate layer (234/240a) is disposed on the second electrode structure (232), and wherein an upper surface of the plate layer (234/240a) is in direct contact with the upper interlayer insulating layer (252a/254).
In regards to claim 3, Lee discloses (See, for example, Fig. 2) that wherein an upper surface of the lower interlayer insulating layer (246/246a) is disposed at a level less than (See, for example, Par [0113[]) an upper end of the polishing stop layer (242/242a).
In regards to claim 4, Lee discloses (See, for example, Fig. 2) that wherein at least a portion of the upper surface of the plate layer (234/240a) is exposed by (See, for example, Fig. 15) the polishing stop layer (242a/242).
In regards to claim 5, Lee discloses (See, for example, Fig. 2) wherein: the plate layer (234/240a) includes tungsten (W) (See, for example, Par [0106]); and the polishing stop layer (242a/242) includes at least one of SiN, SiON, and SiCN (See, for example, Par [0110]).
In regards to claim 6, Lee discloses (see, for example, Fig. 2) wherein the plate layer (234/240a) includes a first upper portion (top horizontal portion of 234/240a) disposed at a higher level than an upper surface of the capacitor (upper surface of 232 (upper electrode)) and extending in a horizontal direction, a first lower portion (bottom horizontal portion of 234/240a) disposed below the first upper portion and extending in the horizontal direction, and a first intermediate portion (vertically positioned portion of 234/240a) connecting the first upper portion (top horizontal portion of 234/240a) to the first lower portion (bottom horizontal portion of 234/240a).
In regards to claim 7, Lee discloses (See, for example, Fig. 2) that wherein: the first upper portion (top horizontal portion of 234/240a) is in direct contact with the upper interlayer insulating layer (252a/254); and the first intermediate portion (vertically positioned portion of 234/240a) is covered by the polishing stop layer (242a/242).
In regards to claim 8, Lee discloses (See, for example, Fig. 2) wherein the first lower portion (bottom horizontal portion of 234/240a) is in direct contact with the polishing stop layer (242a/242) and the lower interlayer insulating layer (246a/246).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee.
In regards to claims 12 and 13, Lee teaches that the metal layer 240 comprises tungsten, and that the polishing stop layer 242 is formed directly upon the metal plate layer 240 and comprises silicon oxynitride, silicon nitride, or SiCN that is, a nitrogen-containing dielectric deposited in direct contact with a tungsten surface. Lee further teaches that following the planarization process, the upper surface of the polishing stop layer pattern 242a, the upper surface of the filling insulation pattern 252a, and the upper surface of the second insulating interlayer pattern 246a are substantially coplanar with one another and are exposed prior to formation of the overlying third insulating interlayers 254. As set forth above with respect to claim 1, the exposed upper surface of the silicon germanium layer 234 within the first openings 250 constitutes an upper surface of the plate layer. Therefore, the process leaves the recited surfaces exposed to ambient conditions between the planarization step and the subsequent deposition of the insulating layer 254.
It is well known in the art of manufacturing semiconductor devices that deposition of a silicon nitride or silicon oxynitride film upon an exposed tungsten surface is conventionally performed using nitrogen-bearing precursors at elevated temperature, and the reaction of such precursors with the underlying tungsten to form an interfacial tungsten nitride is well-understood and predictable consequence of that deposition. It is also well known in the art that silicon germanium and metal continuing surfaces so expose acquire a thin native oxide, and that such a native oxide extends continuously along the exposed surfaces without regard to the identity of the underlying material.
Therefore, Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention that a tungsten nitride layer is formed at the interface between the tungsten metal plate layer 240 and the overlying nitride containing polishing stop layer 242 of Lee, and that a native oxide layer extends along those exposed upper surfaces of the LEE’s device because it is well known in the art of manufacturing semiconductor devices that deposition of a silicon nitride or silicon oxynitride film upon an exposed tungsten surface is conventionally performed using nitrogen-bearing precursors at elevated temperature, and the reaction of such precursors with the underlying tungsten to form an interfacial tungsten nitride is well-understood and predictable consequence of that deposition. It is also well known in the art that silicon germanium and metal continuing surfaces so expose acquire a thin native oxide, and that such a native oxide extends continuously along the exposed surfaces without regard to the identity of the underlying material.
Allowable Subject Matter
Claims 2, 9-11, and 14 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 15 and 20 would be allowable over the prior art of record if amended to overcome the rejection under 112(b) set forth above.
The following is a statement of reasons for the indication of allowable subject matter:
In regards to claim 15, Lee fails to teach or suggest a semiconductor device in which a contact plug extends downward through both the overlying insulating layer and the conductive plate layer itself to reach and touch the underlying electrode structure, such that the lateral wall of that contact plug abuts the plate layer along its passage through it. Lee additionally fails to teach the recited plan-view arrangement in which the polishing stop layer encircles the plate layer. Lee is silent as to a stop layer that laterally surrounds the plate layer when viewed from above.
In regards to claim 20, Lee fails to teach or suggest a polishing stop layer wherein a thickness of the upper portion decreases as a level of the upper portion increases. Lee forms its polishing stop layer as a deposited film substantially uniform thickness upon the metal plate layer, conforming to the topography produced by the step difference between the cell region and the peripheral region. While Lee’s stop layer possesses horizontally and vertically extending portions by virtue of the underlying topography, Lee neither discloses nor suggests an upper portion that grows progressively thinner with increasing vertical level. The recited tapering profile is absent from Lee, and nothing would have suggested including/having such profile to its polishing stop layer.
Claims 16-19 are allowed at least by virtue of their dependency from allowable claim 15.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893
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