DETAILED ACTION
The instant action is in response to application 10 May 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
The specification objections have been withdrawn.
Applicant’s remarks on the merits have been considered. The rejection of claim of claim 13 is sustained. As to claim 13, applicant claims “a third MOSFET connected between the first DC output terminal and in reverse series with each of the first MOSFETs, the third MOSFET located between the capacitor and the first MOSFETs”. Judging by applicant’s arguments, applicant probably meant to specify item 708.
However, that particular interpretation has 112 issues. Note that in applicant’s claims, applicant has referred to “a first MOSFET” and “a second MOSFET” both of which appear to refer to FETS 706a-c and 707a-c”. As point of fact, every MOSFET claimed has referred to a MOSFET per phase, which in a polyphase system is a reasonable interpretation of “a first MOSFET” and “a second MOSFET”. However, since applicant is deliberately changing from one per phase to a single MOSFET, that raises questions about the scope intended. While applicant has support for the amendment, the metes and bounds of the claim must be made clear. Also, whether applicant has intended a single MOSFET or a MOSFET per phase must be made clear. The interpretation of “a mosfet per phase” was given in the initial office action and that interpretation does read on the claim language, especially in light of items 608a-608c. In short, a new 112(b) rejection is required in order to determine individuality or plurality.
As for the interpretation of claim 13, note that applicant previously and currently claimed “a third MOSFET connected between the first DC output terminal and in reverse series with each of the first MOSFETs, the third MOSFET located between the capacitor and the first MOSFETs;”. Note in Figure 5, Li explicitly shows “a third MOSFET (Q9, Q5, Q1) connected between the first DC output terminal (+ CDC) and in reverse series with each of the first MOSFETs (Q2, Q6, Q10), the third MOSFET located between the capacitor (CDC) and the first MOSFETs;”. Note that the interpretation, though probably broader than what applicant intended still meets the claimed language. Though again, applicant probably meant to claim item 708, the language is too broad to be solely interpreted in that manner, and the courts have repeatedly told the office not to read the specification into the claims (See MPEP 2111.01, 2173.01). The anticipation rejection of claim 13 is sustained. Though similar logic could probably be used to anticipate claim 1 as well, in an effort to advance prosecution, a quartet of references has been provided showing that rectifiers having charging switches in reverse series was known in the art at the time of invention and is obvious per MPEP 2144.03
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
As to claim 1, applicant claims “a first MOSFET” referring to a single MOSFET per phase, “a second MOSFET” referring to a single MOSFET per phase and “a third MOSFET” referring to a single MOSFET. This is unclear as to whether applicant intended to claim a single MOSFET or multiple MOSFETs. Rephrased simply, it is unclear if applicant seeks protection for item 708 or for item 608a-c. Singular and plural limitations need to be consistent. For the purposes of examination of claim 1, a MOSFET per phase will be attributed to the first and second MOSFET. A single MOSFET will be attributed to the third MOSFET.
Claim 13 has a similar issue to claim 1. However, the first, second, and third MOSFET will be interpreted to be a MOSFET per phase.
Claims 2-12, 14-18 are dependent upon an indefinite claim and therefore inherit the rejection.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in the United Kingdom on 7 June 2023.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated. (The claims have been condensed.)
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 13-17 (as best understood) are rejected under 35 U.S.C. 102(a)(1) and 102 (a)(2) as being anticipated by Li (US 20220014012).
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As to claim 13, Li discloses A power electronics converter for converting an input AC supply having a plurality of phases to an output DC supply, the converter comprising: a plurality of AC input terminals connectable to the plurality of phases of the input AC supply; first and second DC output terminals; a capacitor connected between the first and second DC output terminals; a first MOSFET connected between each of the plurality of AC input terminals and the first DC output terminal; a second MOSFET connected between each of the plurality of AC input terminals and the second DC output terminal; a third MOSFET connected between the first DC output terminal and in reverse series with each of the first MOSFETs, the third MOSFET located between the capacitor and the first MOSFETs; a switching controller configured to provide switching signals to gates of each of the first, second and third MOSFETs, wherein the controller is configured to operate in a first mode in which pulse width modulated switching signals are provided to the gates of the first and second MOSFETs to convert an AC supply at the AC input terminals to a DC output supply at the DC output terminals while the third MOSFET is switched on, wherein the controller is configured to operate in a second mode during a fault condition in which the first and third MOSFETs are switched off (see image and explanation above in the remarks).
As to claim 14, Li discloses wherein a source of each of the second MOSFETs is connected to the second DC output terminal and a drain of each of the second MOSFETs is connected to a respective one of the AC input terminals (see explanation for claim 3).
As to claim 15, Li discloses wherein a source of each of the third MOSFETs is connected to the first DC output terminal and a drain of each of the third MOSFETs is connected to a drain of a respective one of the first MOSFETs (see claim 3).
As to claim 16, Li discloses further comprising: a fourth MOSFET reverse connected in series with the second MOSFET between the second DC output terminal and each of the plurality of AC input terminals (See Fig. 3, which makes the system symmetrical).
As to claim 17, Li teaches An electrical power system comprising: an electrical machine having a plurality of phases (ASD, 1-2-3); a power electronics converter according to claim 1, the plurality of AC input terminals of which are connected to the plurality of phases of the electrical machine (little a/b/c).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 (as best understood) are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 20220014012).
As to claim 1, Li discloses A power electronics converter for converting an input AC supply having a plurality of phases to an output DC supply, the converter comprising: a plurality of AC input terminals connectable to the plurality of phases of the AC supply; first and second DC output terminals; a capacitor connected between the first and second DC output terminals; a first MOSFET (¶29 “it is recognized that other solid-state semiconductor switches could be used instead, including metal oxide semiconductor field effect transistors (MOSFETs)”) connected between each of the plurality of AC input terminals and the first DC output terminal; a second MOSFET connected between each of the plurality of AC input terminals and the second DC output terminal; provided to the gates of the first and second MOSFETs (¶34 “IGBTs 58 may be selectively gated On and Off during normal operation of the ASD circuit 50, such that current flows through IGBTs 58 in a controlled manner. The operation of rectification circuit 56 in an active or passive/uncontrolled fashion”) to convert an AC supply at the AC input terminals to a DC output supply at the DC output terminals while the third MOSFETs (¶31 “Under normal operating conditions of ASD circuit 50, IGBT 58 of upper switching unit 76 is in an On or conducting state, and thus current also passes through IGBT 58 and to DC capacitor bank 66 connected across DC link 64.”) are switched on, wherein the controller is configured to operate in a second mode (Fig. 7, item 120) during a fault condition in which the first and third MOSFETs are switched off.
Li does not explicitly teach a third MOSFET connected between the first DC output terminal and a node connected to each of the first MOSFETs, the third MOSFET in reverse series with each of the first MOSFETs.
However, this was old and well known at the time of invention and therefore not patentable (See MPEP 2144.03 and US 3872364, Fig. 2, US 4086622 Fig. 1, US 6771521 Fig. 4, and 2015009825 Fig. 3). The expected advantage of having a switch in reverse series with the capacitor would be to prevent unwanted capacitive charging.
As to claim 2, Li discloses wherein the second MOSFETs are also switched off in the second mode (Fig. 7, 120).
As to claim 3, Li discloses wherein a source of each of the first MOSFETs is connected to a respective one of the AC input terminals (see image above, with IGBTs replaced by FETs as described in ¶29).
As to claim 4, Li discloses wherein a source of each of the second MOSFETs is connected to the second DC output terminal and a drain of each of the second MOSFETs is connected to a respective one of the AC input terminals (see explanation for claim 3).
As to claim 5, Li discloses wherein a source of each of the third MOSFETs is connected to the first DC output terminal and a drain of each of the third MOSFETs is connected to a drain of a respective one of the first MOSFETs (see claim 3).
As to claim 6, Li discloses further comprising: a fourth MOSFET reverse connected in series with the second MOSFET between the second DC output terminal and each of the plurality of AC input terminals (See Fig. 3, which makes the system symmetrical).
As to claim 7, Li discloses wherein the AC supply comprises three or more phases (see image below).
As to claim 8, Li discloses wherein the first MOSFET, the second MOSFET and the third MOSFET. He does not explicitly disclose are SiC MOSFETs or GaN MOSFETs. As to claims 24 and 25, According to §MPEP 2144.03, examiner asserts that using silicon carbide wideband semiconductors in power converters is old and well known, and therefore not patentable. See US 2007/0051977 by Saito et al ¶5, US 2006/0113561 by Sankin et al ¶5, US 2008/0123373 by Roesener et al ¶17.
As to claim 9, Li teaches An electrical power system comprising: an electrical machine having a plurality of phases (ASD, three-phases); a power electronics converter according to claim 1, the plurality of AC input terminals of which are connected to the plurality of phases of the electrical machine (little a/b/c).
Claims 10-12, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 20220014012) in view of Chivite Zabalza (US 20230123553).
As to claim 10, Li teaches and an electrical power system comprising an electrical machine (ASD/load) and a power electronics converter according to claim 1.
Li does not explicitly teach An aircraft power and propulsion system comprising: a gas turbine engine; wherein the electrical machine of the electrical power system is mechanically coupled with a spool of the gas turbine engine.
Chivite Zabalza teaches An aircraft power and propulsion system comprising: a gas turbine engine (201); wherein the electrical machine (213, 216) of the electrical power system is mechanically coupled with a spool of the gas turbine engine (¶29 “there is provided an aircraft power and propulsion system comprising: a gas turbine engine; and an electrical power system according to the first aspect. The electrical machine of the electrical power system is mechanically coupled with a spool of the gas turbine engine.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use mechanical coupling as disclosed in Li to provide redundant means of energy.
As to claim 11, Li in view of Chivite Zabalza teaches An aircraft (¶29) comprising the electrical power system of claim 9.
As to claim 12, Li in view of Chivite Zabalza teaches wherein the aircraft is a hybrid electric aircraft (Fig. 2A).
As to claim 18, this is similar to claim 9 above with fewer limitations and is obvious for similar reasons.
Conclusion
Examiner has cited particular column, paragraph, and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M NOVAK whose telephone number is (571)270-1375. The examiner can normally be reached on 9AM-5PM,Monday through Thursday, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached on 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER M NOVAK/ Primary Examiner, Art Unit 2839
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