Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/660,465 filed on 05/10/2024.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 is rejected because it is unclear what is meant by “an upper layer and a lower layer of the insulating material layer are both semiconductor material layers.” Specifically, the claim first recites an “intermediate insulating material layer,” but then states that the upper and lower layers of the insulating material layer are semiconductor material layers. It is therefore unclear whether the semiconductor material layers are part of the insulating material layer itself or whether the applicant intended to recite semiconductor material layers disposed above and below the intermediate insulating material layer. Accordingly, the metes and bounds of the claim are unclear.
Claims 3-4 are rejected under 35 U.S.C. 112(b) as being indefinite. Claim 3 recites “a pixel circuit layer” and “a drive circuit layer,” whereas claim 1 recites “a pixel circuit” and “a drive circuit.” It is unclear whether the recited “pixel circuit layer” and “drive circuit layer” correspond to the previously recited “pixel circuit” and “drive circuit,” or whether they represent different structural elements. Furthermore, the specification does not appear to distinguish the recited “pixel circuit layer” and “drive circuit layer” from the previously recited “pixel circuit” and “drive circuit.” Accordingly, applicant is required to clarify the scope of the claims by using consistent terminology or by expressly defining the relationship between these elements.
For purposes of examination, the examiner interprets the recited “pixel circuit layer” and “drive circuit layer” as corresponding to the previously recited “pixel circuit” and “drive circuit,” respectively.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pub # 2018/0211596 to Gu.
Regarding independent claim 1, Gu discloses a stacked micro-display structure (Fig. 3: ¶0034-0038; under BRI, the disclosed integrated OLED display apparatus constitutes the claimed stacked micro-display structure), comprising:
a substrate (312);
wherein a first surface of the substrate (312) is provided with a pixel circuit (314); and
a second surface, opposite to the first surface, of the substrate is provided with a drive circuit (308).
Regarding claim 2, Gu disclose wherein the substrate (312) has a sandwich structure and comprises an intermediate insulating material layer (310 and 318); and an upper layer (318) and a lower layer (310) of the insulating material layer are both semiconductor material layers (¶0034-0035).
Regarding claim 3, Gu disclose wherein a pixel circuit layer (314) on the first surface of the substrate (312) and a drive circuit layer (308) on the second surface of the substrate (312) are connected by interconnects (316).
Regarding claim 4, Gu disclose wherein an anode electrode (324 and ¶0036) is on the pixel circuit layer (314), and a light-emitting layer (326) and a cathode (328) are on the anode electrode (324).
Regarding claim 5, Gu disclose wherein an encapsulation layer (330) is on the pixel circuit layer (314).
Regarding claim 6, Gu disclose wherein a carrier (under BRI, 306 is considered to be a carrier) is disposed under the drive circuit layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2018/0211596 to Gu in view of US Pub # 2023/0069107 to Wei.
Regarding claim 7, Gu disclose a manufacturing process (Figs. 4A-4B, 6A-6B and 8A-8B) for the stacked micro-display structure according to claim 1, comprising: step 1) preparing the substrate (312); step 2) manufacturing a drive circuit layer (308) on the second surface, facing upward, of the substrate; and attaching the drive circuit layer (308) to a carrier (306); step 4) manufacturing a pixel circuit layer (314) on the first surface of the substrate; step 5) manufacturing via holes (316 and ¶0037); step 6) manufacturing interconnects (316); step 7) manufacturing an anode electrode (324); and step 8) manufacturing a light-emitting layer (326) and a cathode (328); and manufacturing an encapsulation layer (330).
Gu does not expressly disclose step 3) turning the substrate.
Wei teaches turning the substrate over (Figs. 5A-5C and Fig. 7). Wei specifically teaches a flip-and-bond fabrication technique in which an original substrate, including a semiconductor device layer and interconnect layers formed above the semiconductor device layer, is flipped and bonded to a carrier substrate through a top interconnect layer (¶0047-0052).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to modify the manufacturing process of Gu by turning over Gu’s substrate and positioning the previously formed drive-circuit side toward the carrier before attachment, as taught by Wei. Such a modification would have predictably oriented and supported the circuit-bearing surface while permitting subsequent processing of the opposite surface of the substrate.
Regarding claim 8, Gu disclose wherein the substrate in the step 1) is a silicon-on-insulator (SOI) wafer (Figs. 2A-2C and ¶0035).
Regarding claim 9, Gu disclose all of the limitations of claim 8 from which this claim depends.
As discussed above with respect to claim 7, Gu teaches a manufacturing process for a stacked micro-display structure, including preparing a substrate, manufacturing a drive circuit layer, manufacturing a pixel circuit layer, manufacturing via holes, manufacturing interconnects, manufacturing an anode electrode, manufacturing a light-emitting layer and a cathode, and manufacturing an encapsulation layer. Gu further teaches the substrate is a silicon-on-insulator (SOI) wafer, as recited in claim 8.
Gu, however, does not expressly disclose turning the substrate over prior to attaching the drive circuit layer to a carrier and subsequently thinning the first surface of the SOI wafer during the manufacturing process.
Wei teaches (Figs. 2A-2C and ¶0035) turning (flipping/inverting) a substrate having circuitry formed thereon, attaching the circuit-bearing surface to a carrier, and thinning the substrate from the opposite surface during backside processing.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to modify the manufacturing process of Gu by turning the substrate over, attaching the drive-circuit side to a carrier, and thinning the first surface of the SOI wafer as taught by Wei, because such processing provides mechanical support during backside fabrication, facilitates subsequent processing of the opposite surface, and reduces substrate thickness to enable formation of backside features while minimizing wafer damage and improving manufacturability (¶0063 and ¶0050).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2018/0211596 to Gu in view of US Pub # 2023/0069107 to Wei and further in view of US Pat # 8,222,139 to Chen et al. (Chen).
Regarding claim 10, Gu disclose all of the limitations of claim 7 from which this claim depends.
As discussed above with respect to claim 7, Gu as previously modified teaches forming via holes and interconnects that electrically connect the pixel circuit with the drive circuit (see the rejection of claim 7). Gu as previously modified, however, does not expressly disclose filling the via holes using tungsten or copper by metal deposition and chemical mechanical polishing (CMP).
Chen teaches forming TSV/interconnect structures (Fig. 3: 18) by filling via openings with copper or tungsten (Fig. 4: 22 or 24), using metal seed layer deposition and copper plating to fill the vias, followed by chemical mechanical polishing (CMP) to complete the interconnect structure (see corresponding paragraphs for Figs. 4-5).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to employ the metal deposition and CMP techniques taught by Chen in the manufacturing process of Gu to form the via interconnects because these were well-known semiconductor fabrication techniques for producing reliable, planar, conductive TSV/interconnect structures, reducing process costs (col. 5, lines 1-10).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub # 2019/0035817 to Park, US Pub # 2013/0112960 to Chaji et al.
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/MOHSEN AHMADI/ Primary Examiner, Art Unit 2896
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