DETAILED ACTION
This correspondence is in response to the communications received May 10, 2024. Claims 1-8 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
The abstract of the disclosure is objected to because the abstract exceeds 150 words at the current 154 words. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Relevant Prior Art
Kakumu et al. (US 2024/0404583) Fig. 1, shown below.
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Harada et al. (US 2024/0179886) Figs. 7A-7B, shown below.
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Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Fig. 1A, 2MB and 2MC, a semiconductor device including a memory element (“As for the memory cell, the electric potential of the second Si layer 22aa that serves as the channel of the MOS transistor that includes the N+ layers 30a and 30b and the TiN-layer 34 of the gate is controlled due to the holes (the holes 8b in Fig. lA, Fig. 1B, Fig. 1C, and Fig. 1D) that correspond to the signal charges that are stored in the first Si layer 20a with certainty. As a result, the memory cell that has a large difference between "1" and "0" signals is obtained.”, ¶ 0041. Therefore, it is understood that the memory functionality occurs in the stored charge in the columnar material layer 20a.), comprising:
a first semiconductor layer (3a, ¶ 0016, or 20a) that is erected above a substrate (1, ¶ 0016) in a direction perpendicular to the substrate (3a vertically over 1) and that is columnar (shown in Fig. 1A);
a first impurity region (N-type impurity region 2a) that is connected to a bottom portion of the first semiconductor layer (lower surface of 3a);
a first gate insulating layer (5a, ¶ 0017) that is in contact with a side surface of the first semiconductor layer (5a is in contact with side surface of 3a);
a first gate conductor layer (6a) that is in contact with the first gate insulating layer (in contact with 5a);
a first insulating layer (4a, ¶ 0017) that insulates the first impurity region (2a) and the first gate conductor layer from each other (4a insulates 2a from 6a);
a second semiconductor layer (“second Si layer 22aa”, ¶ 0033) that includes a bottom portion (lower surface of 22aa) that is in contact with a top of the first semiconductor layer (lower surface of 22aa is in contact with the top surface of 2a);
a second insulating layer (15) that is on the first gate conductor layer (on 6a) and that surrounds a vicinity of a boundary between the first semiconductor layer and the second semiconductor layer (15 vertically overlaps and is around the interface between 2a and 3a);
a second gate insulating layer (33) that is in contact with the second semiconductor layer (22aa);
a second gate conductor layer (34) that is in contact with the second gate insulating layer (33); and
a second impurity region (30a) and a third impurity region (30b) that are along both edges of the second semiconductor layer (at lateral edges of 22aa) in a first direction (x direction) in a plan view (can be seen from above),
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wherein positions of both edges of the top of the first semiconductor layer (20a) in a second direction (y direction) perpendicular to the first direction (x direction) are outside positions of both edges of the bottom portion of the second semiconductor layer in a plan view (this orientation can be seen in Fig. 2MC, shown below where the top surface of 20a is as wide as W1, whereas the width of 22a is as wide as W2, in the y direction, where W1 is wider than W2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 5, 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Harada et al. (US 2024/0349481).
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Regarding claim 1, the prior art of Harada discloses in Figs. 4A-4B, a semiconductor device including a memory element (see title, “SEMICONDUCTOR DEVICE INCLUDING MEMORY ELEMENT”), comprising:
a first semiconductor layer (“first pillar P-layer 3a (an example of a “first semiconductor pillar” in the claims) that contains acceptor impurities (a semiconductor region that contains acceptor impurities is referred to below as a “P-layer”, ¶ 0026. Where semiconductor pillar 3a is equivalent to “first pillar P-layer 3aa”, ¶ 0041) that is erected above a substrate (3aa is above “substrate 1”, ¶ 0026) in a direction perpendicular to the substrate and that is columnar (3aa extends vertically above 1);
a first impurity region (“N-layer 2 (an example of a “first impurity region” in claims) that contains donor impurities (a semiconductor region that contains donor impurities is referred to below as an “N-layer”).”, ¶ 0026) that is connected to a bottom portion of the first semiconductor layer (2 connects to 3aa);
a first gate insulating layer (“gate insulating layer 5a”, ¶ 0026) that is in contact with a side surface of the first semiconductor layer (5a contacts side surfaces of 3aa);
a first gate conductor layer (“first gate conductor layer 6a”, ¶ 0026) that is in contact with the first gate insulating layer (6a in contact with 5a);
a first insulating layer (“insulating layer 4a”, ¶ 0026) that insulates the first impurity region and the first gate conductor layer from each other (4a insulates 2 from 6a);
a second semiconductor layer (“P-layer 3b (an example of a “second semiconductor pillar” in the claims)”, ¶ 0026. Where 3b is equivalent to “second pillar P-layer 3ba”, ¶ 0041) that includes a bottom portion (lower surface of 3ba) that is in contact with a top of the first semiconductor layer (lower surface of 3ba is in contact with the top surface of 3aa);
a second insulating layer (“second insulating layer 4b”, ¶ 0026.) that is on the first gate conductor layer (4b on 6a) and that surrounds a vicinity of a boundary between the first semiconductor layer and the second semiconductor layer (4b surrounds the boundary between 3aa and 3ba);
a second gate insulating layer (“gate insulating layer 9”, ¶ 0026) that is in contact with the second semiconductor layer (9 is in contact with 3ba);
a second gate conductor layer (“gate conductor layer 10”, ¶ 0026) that is in contact with the second gate insulating layer (10 is in contact with 9); and
a second impurity region (“N.sup.+-layer 11a (an example of a “second impurity region”, ¶ 0026) and a third impurity region (“N.sup.+-layer 11b (an example of a “third impurity region””, ¶ 0026) that are along both edges of the second semiconductor layer in a first direction in a plan view (11a, 11b are formed at edges of 3ba in plan view, into the page direction of Fig. 4A, and vertical direction of Fig. 4B, hereinafter referred to as ‘FD’),
wherein positions of both edges of the top of the first semiconductor layer (3aa’s edges that form width W1) in a second direction (lateral direction for both Figs. 4A and 4B, hereinafter referred to as ‘SD’) perpendicular to the first direction (SD is perpendicular to FD) are outside positions of both edges of the bottom portion of the second semiconductor layer in a plan view (3aa’s edges that form W1 are outside positions of the edges of 3ba which form width W2).
Harada’s teachings of Figs. 4A-4B in ¶ 0041, do not explicitly state that 3aa and 3ba are semiconductor material, and thus do not explicitly disclose, “a first semiconductor layer … a second semiconductor layer”.
Harada’s teachings of Fig. 1A-1B in ¶ 0026, which are essentially the same device as Figs. 4A-4B with slightly different geometries, do show that equivalent layers to 3aa and 3ba are semiconductor materials, “first pillar P-layer 3a (an example of a “first semiconductor pillar” in the claims) that contains acceptor impurities (a semiconductor region that contains acceptor impurities is referred to below as a “P-layer” and, “(“P-layer 3b (an example of a “second semiconductor pillar” in the claims)”.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of, “a first semiconductor layer … a second semiconductor layer”, as disclosed by the embodiment of Figs. 1A-1B of Harada in the system of the embodiment of Figs. 4A-4B of Harada, for the purpose of utilizing semiconductor materials which are the computing industry standard material for integrated circuit devices which can be doped to function in a switching manner to carry out various processes that include memory devices. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 2, the prior art of Harada discloses the semiconductor device according to claim 1, wherein the first gate conductor layer is connected to a plate line (“first gate conductor layer 6a is connected to a first plate line PL1”, ¶ 0027), wherein the second gate conductor layer is connected to a word line (“gate conductor layer 10 is connected to a word line WL”, ¶ 0027), wherein the first impurity region is connected to a control line (“N-layer 2 is connected to a control line CL”, ¶ 0027), wherein the second impurity region is connected to a source line (“N.sup.+-layer 11a is connected to a source line SL”, ¶ 0027), and wherein the third impurity region is connected to a bit line (“N.sup.+-layer 11b is connected to a bit line BL”, ¶ 0027).
Regarding claim 4, the prior art of Harada discloses the semiconductor device according to claim 1, wherein the first gate conductor layer is divided into multiple gate conductor layers in a plan view, and the divided gate conductor layers are driven by applying a synchronous or asynchronous voltage thereto (6a can be operated as both 6a and 6b, “the first gate conductor layer 6a and the second gate conductor layer 6b may be divided into multiple pieces in the horizontal or perpendicular direction, and these may be synchronously or asynchronously driven.”, ¶ 0058).
Regarding claim 5, the prior art of Harada discloses the semiconductor device according to claim 1, wherein the first impurity region is isolated from an adjacent memory cell (“in a plan view, the N-layers 2 of memory cells that are aligned on a line may be connected to each other and may be electrically isolated from the N-layer of a memory cell that is adjacent to the N-layers 2 connected to each other and that is connected on the line”, ¶ 0055), and wherein the third impurity region that has conductivity opposite that of the first impurity region is in contact with a bottom of the first impurity region (“an impurity region a conductivity type of which is opposite that of the first impurity region may be in contact with a bottom of the first impurity region”, ¶ 0013).
Regarding claim 7, the prior art of Harada discloses the semiconductor device according to claim 1, wherein the first gate conductor layer is divided into multiple gate conductor layers in a plan view, and the divided gate conductor layers are synchronously or asynchronously driven (6a can be operated as both 6a and 6b, “the first gate conductor layer 6a and the second gate conductor layer 6b may be divided into multiple pieces in the horizontal or perpendicular direction, and these may be synchronously or asynchronously driven.”, ¶ 0058).
Regarding claim 8, the prior art of Harada discloses the semiconductor device according to claim 1, wherein a voltage that is applied to the first to third impurity regions and the first and second gate conductor layers is controlled (“a voltage that is applied to the first to third impurity regions and the first to third gate conductor layers may be controlled”, ¶ 0014), an electric current is caused to flow through the second semiconductor layer between the second impurity region and the third impurity region (“electric current that is caused to flow through the second semiconductor pillar between the second impurity region and the third impurity region”, ¶ 0014), and a data writing operation is performed such that a majority carrier in electrons and holes that are generated in the second semiconductor layer due to an impact ionization phenomenon or a gate-induced drain leakage (GIDL) current is mainly stored in the first semiconductor layer by using the electric current (“a data writing operation may be performed such that a majority carrier in electrons and holes that are generated in the second semiconductor pillar due to an impact ionization phenomenon or a gate induced drain leak current is mainly stored in the first semiconductor pillar by using an electric current”, ¶ 0014), and a data wiping operation is performed such that the majority carrier that is stored in the first semiconductor layer is discharged from the first semiconductor layer (“data wiping operation may be performed such that the majority carrier that is stored in the first semiconductor pillar is discharged from the first semiconductor pillar”, ¶ 0014).
Allowable Subject Matter
Claims 3 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
“3. The semiconductor device according to Claim 1, wherein positions of both edges of the second gate conductor layer in the first direction and the second direction substantially match positions of both edges of the second semiconductor layer in a plan view, and wherein a metal wiring layer is in contact with the second gate conductor layer and extends in the second direction.” This is not shown by the Fig. 4A embodiment of Harada, because the shape of the second semiconductor layer 3ba, which shortens the width of 10 due to 3ba’s u-shape.
“6. The semiconductor device according to The semiconductor device according to wherein the first impurity region extends in a direction in which the word line extends in a plan view, is shared with an adjacent memory cell that is located in the direction in which the word line extends, and is isolated from an adjacent memory cell that is located in a direction perpendicular to the direction in which the word line extends.”
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893
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