DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 05/09/2025, 09/16/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature “…bandwidth during read of at least 2.7TB/s…power efficiency of no greater than 1.1 pJ/bit”, as recited claims 1, 9, 17, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
Regarding Independent Claims 1, 9 and 17 states that “has a bandwidth during read of at least 2.7 TB/s and …has a power efficiency of no greater than 1.1 pJ/bit”.
MPEP 2173.05(g) states, “[W]hen claims merely recite a description of a problem to be solved or a function or result achieved by the invention, the boundaries of the claim scope may be unclear.” Additionally, MPEP 2173.05(g) instructs examiners as follows:
Notwithstanding the permissible instances, the use of functional language in a claim may fail "to provide a clear-cut indication of the scope of the subject matter embraced by the claim" and thus be indefinite. In re Swinehart, 439 F.2d 210, 213 (CCPA 1971). For example, when claims merely recite a description of a problem to be solved or a function or result achieved by the invention, the boundaries of the claim scope may be unclear. Halliburton Energy Servs., Inc. v. M-I LLC, 514 F.3d 1244, 1255, 85 USPQ2d 1654, 1663 (Fed. Cir. 2008) (noting that the Supreme Court explained that a vice of functional claiming occurs "when the inventor is painstaking when he recites what has already been seen, and then uses conveniently functional language at the exact point of novelty") (quoting General Elec. Co. v. Wabash Appliance Corp., 304 U.S. 364, 371 (1938)); see also United Carbon Co. v. Binney & Smith Co., 317 U.S. 228, 234, 55 USPQ 381 (1942) (holding indefinite claims that recited substantially pure carbon black "in the form of commercially uniform, comparatively small, rounded smooth aggregates having a spongy or porous exterior"). Further, without reciting the particular structure, materials or steps that accomplish the function or achieve the result, all means or methods of resolving the problem may be encompassed by the claim. Ariad Pharmaceuticals., Inc. v. Eli Lilly & Co., 598 F.3d 1336, 1353, 94 USPQ2d 1161, 1173 (Fed. Cir. 2010) (en banc). See also Datamize LLC v. Plumtree Software Inc., 417 F.3d 1342, 75 USPQ2d 1801 (Fed. Cir. 2005) where a claim directed to a software based system for creating a customized computer interface screen recited that the screen be "aesthetically pleasing," which is an intended result and does not provide a clear cut indication of scope because it imposed no structural limits on the screen. Unlimited functional claim limitations that extend to all means or methods of resolving a problem may not be adequately supported by the written description or may not be commensurate in scope with the enabling disclosure, both of which are required by 35 U.S.C. 112(a) and pre-AIA 35 U.S.C. 112, first paragraph. In re Hyatt, 708 F.2d 712, 714, 218 USPQ 195, 197 (Fed. Cir. 1983); Ariad, 598 F.3d at 1340, 94 USPQ2d at 1167. For instance, a single means claim covering every conceivable means for achieving the stated result was held to be invalid under 35 U.S.C. 112, first paragraph because the court recognized that the specification, which disclosed only those means known to the inventor, was not commensurate in scope with the claim. Hyatt, 708 F.2d at 714-715, 218 USPQ at 197. For more information regarding the written description requirement and enablement requirement under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, see MPEP §§ 2161-2164.08(c). Examiners should keep in mind that whether or not the functional limitation complies with 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph, is a different issue from whether the limitation is properly supported under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, or is distinguished over the prior art.
This "2.7TB/s" read bandwidth is a pure result, and the question for applicant is, what does the invention require in order to achieve this result. In other words, what inside the claim does the claimed "apparatus" have that yields the result of 2.7TB/s. The same applies to the claimed power efficiency of no greater than 1.1pJ/bit. Therefore, claims 1, 9 and 17 are indefinite because it recited the limitations directed to only the result achieved. Dependent claims 2, 10, 18, and 19, are also rejected for the same reasons of reciting the result of “at least 3TB/second” or “power efficiency no greater than 1 pJ/bit.” The claim lacks the necessary structure that accomplishes this result. MPEP 2173.05(g).
Claims 2-8, 10-16, 18-20 depend from claim 1, 9, 17 are rejected for inheriting this deficiency.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 9-10, 17-19 are rejected under both 35 U.S.C. 102(a)(1) as being anticipated by Dally et al (US 11,977,766 B2 hereinafter “Dally”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Dally, for example in Figs. 1-6, discloses an apparatus (see for example in Fig. 1A related in Figs. 1B-6) comprising: a memory system (e.g., 200; in Fig. 2A related in Figs. 1, 3-6) comprising a plurality of memory die (e.g., memory die; in Fig. 1A related in Figs. 1B-6), each die of the plurality of memory die comprising a memory array with a plurality of non-volatile memory cells (see for example in Figs. 1-6; Col. 7, lines 38-42; Col. 14, lines 10+; Col. 29, lines 4+), wherein; the memory system has a bandwidth during read of at least 2.7 TB/s (e.g., 16SMs 440 with 6.4 TBytes/sec; in Fig. 4C related in Figs. 1-3, 5-6 and see MPEP 2173.05(g) as discussed above), and each memory array has a power efficiency of no greater than 1.1 pJ/bit (e.g., reducing the memory access energy to 0.5pJ/bit or 500 fJ/bit or 80 fJ/bit; see Col. 3, line 4; Col. 10, line 66, and see MPEP 2173.05(g) as discussed above).
Regarding claim 2, Dally, for example in Figs. 1-6, discloses wherein the memory system has a bandwidth of at least 3 TB/s (e.g., 16SMs 440 with 6.4 TBytes/sec; in Fig. 4C related in Figs. 1-3, 5-6 and see MPEP 2173.05(g) as discussed above) and wherein each array has a power efficiency of no greater than 1 pJ/bit (e.g., reducing the memory access energy to 0.5pJ/bit or 500 fJ/bit or 80 fJ/bit; see Col. 3, line 4; Col. 10, line 66, and see MPEP 2173.05(g) as discussed above).
Regarding Independent Claim 9, Dally, for example in Figs. 1-6, discloses a computer system (see for example in Figs. 5B-5C related in Figs. 1-4, 6), comprising: a single processing unit (e.g., processor 110; in Figs. 1A, 1C related in Figs. 2-6); a plurality of high bandwidth flash (HBF) packages in electrical communication with the single processing unit (as show in Fig. 1 related in Figs. 2-6), each of the HBF packages having a plurality of memory dies with arrays of memory cells (within the memory die 120; in Figs. 1A and 1B related in Figs. 2-6); wherein the HBF packages have a combined bandwidth during read with the single processing unit of at least 2.7 TB/s (e.g., 16SMs 440 with 6.4 TBytes/sec; in Fig. 4C related in Figs. 1-3, 5-6 and see MPEP 2173.05(g) as discussed above); and wherein the dies have a power efficiency of no greater than 1.1 pJ/bit (e.g., reducing the memory access energy to 0.5pJ/bit or 500 fJ/bit or 80 fJ/bit; see Col. 3, line 4; Col. 10, line 66, and see MPEP 2173.05(g) as discussed above).
Regarding claim 10, Dally, for example in Figs. 1-6, discloses wherein the HBF packages have a combined bandwidth with the single processing unit of at least 3 TB/second (e.g., 16SMs 440 with 6.4 TBytes/sec; in Fig. 4C related in Figs. 1-3, 5-6 and see MPEP 2173.05(g) as discussed above) and wherein each array has a power efficiency of no greater than 1 pJ/bit (e.g., reducing the memory access energy to 0.5pJ/bit or 500 fJ/bit or 80 fJ/bit; see Col. 3, line 4; Col. 10, line 66, and see MPEP 2173.05(g) as discussed above).
Regarding Independent Claim 17, Dally, for example in Figs. 1-6, discloses a method of operating a computing system (see for example in Figs. 5B-5C related in Figs. 1-4, 6), comprising the steps of: preparing a processing unit (e.g., processor 110; in Figs. 1A, 1C related in Figs. 2-6) and a plurality of high bandwidth flash (HBF) packages, the HBF packages being in electrical communication with the processing unit (as show in Fig. 1 related in Figs. 2-6), each of the HBF packages having a plurality of memory dies with arrays of memory cells (within the memory die 120; in Figs. 1A and 1B related in Figs. 2-6); and performing a large language model processing operation where data is transmitted between the HBF packages and the processing unit at a rate that is greater than 2.7 TB/s (e.g., 16SMs 440 with 6.4 TBytes/sec; in Fig. 4C related in Figs. 1-3, 5-6 and see MPEP 2173.05(g) as discussed above).
Regarding claim 18, Dally, for example in Figs.1-6, discloses wherein data is transmitted between the HBF packages and the processing unit at a rate that is greater than 3 TB/s (e.g., 16SMs 440 with 6.4 TBytes/sec; in Fig. 4C related in Figs. 1-3, 5-6 and see MPEP 2173.05(g) as discussed above).
Regarding claim 19, Dally, for example in Figs. 1-6, discloses wherein each of the arrays has a power efficiency of no greater than 1 pJ/bit (e.g., reducing the memory access energy to 0.5pJ/bit or 500 fJ/bit or 80 fJ/bit; see Col. 3, line 4; Col. 10, line 66, and see MPEP 2173.05(g) as discussed above).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3-6, 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Dally et al (US 11,977,766 B2 hereinafter “Dally”) in view of Lee et al (US 9,245,639 B1 hereinafter “Lee”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding claim 3, Dally, for example in Figs. 1-6, discloses the claimed invention as discussed above. However, Dally is silent with regard to at least thirty-two planes.
In the same field of endeavor, Lee, for example in Figs. 1-6, discloses at least thirty-two planes (e.g., multiple planes with string size of 32 cells; in Figs. 1-2, 4-6).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Dally such as hierarchical network for stacked memory system (see for example in Figs. 1-6 of Dally) by incorporating the teaching of Lee such as NAND flash memory array architecture having low read latency and low program disturb (see for example in Figs. 1-6 of Lee), for the purpose of controlling the reduction in latency is achieved by a NAND memory array architecture which employs a small NAND string, a dual plane interleaved memory architecture, a partitioned NAND array, selectively coupled local bit lines per each global bit line, and a counter-biasing mechanism to avoid inadvertent programming and program disturb (Lee, see Abstract).
Regarding claim 4, the above Dally/Lee, the combination discloses wherein each plane of the memory die with at least thirty-two planes includes two sub-planes (see for example in Figs. 1-6 of Dally and also see in Figs. 1-6 of Lee, as discussed above).
Regarding claim 5, the above Dally/Lee, the combination discloses wherein each plane has a physical page size that is no greater than 4 kB (see for example in Figs. 1-6 of Dally and also see in Figs. 1-6 of Lee, as discussed above).
Regarding claim 6, the above Dally/Lee, the combination discloses wherein each plane has a physical page size that is no greater than 2 kB (see for example in Figs. 1-6 of Dally and also see in Figs. 1-6 of Lee, as discussed above).
Regarding claim 11, the above Dally/Lee, the combination discloses wherein at least one memory die of the plurality of memory dies has at least thirty-two planes (see for example in Figs. 1-6 of Dally and also see in Figs. 1-6 of Lee, as discussed above).
Regarding claim 12, the above Dally/Lee, the combination discloses wherein each plane of the memory die with at least thirty-two planes includes two sub-planes (see for example in Figs. 1-6 of Dally and also see in Figs. 1-6 of Lee, as discussed above).
Regarding claim 13, the above Dally/Lee, the combination discloses wherein each plane has a physical page size that is no greater than 4 kB (see for example in Figs. 1-6 of Dally and also see in Figs. 1-6 of Lee, as discussed above).
Regarding claim 14, the above Dally/Lee, the combination discloses wherein each plane has a physical page size that is no greater than 2 kB (see for example in Figs. 1-6 of Dally and also see in Figs. 1-6 of Lee, as discussed above).
Claims 7-8, 15-16, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Dally et al (US 11,977,766 B2 hereinafter “Dally”) in view of Shimizu et al (US 11,881,282 B2 hereinafter “Shimizu”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding claim 7, Dally, for example in Figs. 1-6, discloses the claimed invention as discussed above. However, Dally is silent with regard to supply voltages that are no greater than 1.5 V.
In the same field of endeavor, Shimizu, for example in Figs. 1-7, discloses to supply voltages that are no greater than 1.5 V (e.g., external voltage 1 or Vext1 approximately 1.2V).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Dally such as hierarchical network for stacked memory system (see for example in Figs. 1-6 of Dally) by incorporating the teaching of Shimizu such as memory device with detection of out-of-range operating temperature (see for example in Figs. 1-7 of Shimizu), for the purpose of controlling the memory die also including an externally-powered thermometer to: determine a first/second measured operating temperature value of the memory die (Shimizu, see Abstract).
Regarding claim 8, the above Dally/Shimizu, the combination discloses wherein the supply voltages are no greater than 1.2 V (see for example in Figs. 1-6 of Dally and also see in Figs. 1-7 of Shimizu, as discussed above).
Regarding claim 15, the above Dally/Shimizu, the combination discloses wherein the memory dies have supply voltages that are no greater than 1.5 V (see for example in Figs. 1-6 of Dally and also see in Figs. 1-7 of Shimizu, as discussed above).
Regarding claim 16, the above Dally/Shimizu, the combination discloses wherein the memory dies have supply voltages that are no greater than 1.2 V (see for example in Figs. 1-6 of Dally and also see in Figs. 1-7 of Shimizu, as discussed above).
Regarding claim 20, the above Dally/Shimizu, the combination discloses wherein the memory dies have supply voltages of no greater than 1.2 V (see for example in Figs. 1-6 of Dally and also see in Figs. 1-7 of Shimizu, as discussed above).
Applicant are reminded that when presenting amendments to claims. In order to be fully responsive, an attempt should be made to point out the patentable novelty (see MPEP 714.04). Additionally, Applicant should point out where and/or how the originally filed disclosure supports the amendment(s) (see MPEP 2163 (II)(A)).
Conclusion
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/THA-O H BUI/Primary Examiner, Art Unit 2825 11/24/2025