DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claims 1 and 4-5 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim U.S. Patent Application Publication 2025/0118616 A1 (the ‘616 reference).
The reference discloses in Fig. 2, para [16] (paragraph(s) [0016]) and other text an electronic package as claimed.
Referring to claim 1, the ‘616 reference discloses an electronic package, comprising:
a carrier structure (100) having a circuit layer;
an electronic element (semiconductor chip 200) disposed on the carrier structure (100) and electrically connected to the circuit layer;
a heat dissipation structure (300) disposed on the carrier structure (100) and covering the electronic element (200), wherein the heat dissipation structure (300) has a plurality of convex portions (not labeled) facing the carrier structure (100); and
a cladding layer (molding layer MD) formed on the carrier structure (100) and covering the electronic element (200).
Referring to claim 4, Fig. 2 depicts that the heat dissipation structure (300) includes a heat dissipation sheet (a horizontal portion), and the convex portions (the not-labeled portions) are disposed on the heat dissipation sheet.
Referring to claim 5, the reference further discloses conductive elements (500, para [19]) electrically connected to the carrier structure (100).
3. Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ishii et al. CN 2008305958 A, Semiconductor Device, Published December 18, 2008, the following rejections are based on an English translation by USPTO-PE2E.
Ishii discloses in Fig. 5(e) (reproduced below, with labels, such as “convex portions”, added by the examiner for ease of explanation) and related text an electronic package as claimed.
Referring to claim 1, Ishii discloses an electronic package, comprising:
a carrier structure (wiring substrate 21, page 4, 5th full paragraph) having a circuit layer;
an electronic element (semiconductor element 22, page 4, 4th full paragraph) disposed on the carrier structure (21) and electrically connected to the circuit layer;
a heat dissipation structure (heat spreader 26, page 5, first full paragraph) disposed on the carrier structure (21) and covering the electronic element (22), wherein the heat dissipation structure (26) has a plurality of convex portions (“convex portions”) facing the carrier structure (21); and
a cladding layer (sealing resin 25, page 5, 2nd full paragraph) formed on the carrier structure (21) and covering the electronic element (22).
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Referring to claim 2, Ishii further discloses that one of the convex portions (“convex portions”) is located at at least one corner of the cladding layer (25).
Referring to claim 3, Ishii further discloses that the heat dissipation structure (26) is made of metal (such as copper, page 5, 1st full paragraph).
Referring to claim 4, Fig. 5e, reproduced above, depicts that the heat dissipation structure (26) includes a heat dissipation sheet (“heat dissipation sheet”), and the convex portions (“convex portions”) are disposed on the heat dissipation sheet.
Referring to claim 5, Ishii further discloses conductive elements (solder balls 24, page 4, last paragraph) electrically connected to the carrier structure (21).
Allowable Subject Matter
4. Claims 6-10 are allowable over the prior art of record.
The following is an examiner's statement of reasons for allowance: The prior art of record fails to teach or render obvious a method of manufacturing an electronic package with all limitations as recited in claim 6, which may be characterized in performing a singulation process along a cutting path, and in that the cutting path passes through the plurality of convex portions.
Conclusion
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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06-15-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818
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