DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 10, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement (IDS) submitted on September 27, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
Note: Examiner makes the following observations of record upon reading the “summary” section of the specification:
First observation: Typically or conventionally in the art of semiconductor memory, a multi-bit memory cell is described as storing N bits with N being an integer greater than or equal to two such that the cell can be in any one of 2N states or levels including a non-programmed state and 2N-1 programmed states; however, in the instance of this Application, the inventor uses a different paradigm or unusual alternative way of describing such a multi-bit memory cell, wherein the inventor describes the memory cell as being in any one of N states or levels, N being even and greater than two. Hence, inherently then such a cell would store M bits, wherein M = log2N.
Second observation: It is typical or conventional in the art of semiconductor memory that a bit of data is referred to as a datum since it is the smallest piece or unit of digital data, and a plurality of bits is referred to as data; however, in the instance of this Application, the inventor seems to use the word “datum” to be the collection of bits stored in a memory cell. For example, the four bits having value 1111 stored in a memory cell seems to be a datum in the context of at least some portions of the specification. Hence, Applicant is using a different definition of datum and must therefore be cautious when using the word “data” when referring to a plurality since Applicants singular term of datum now has a definition that depends on how many bits are being stored in each memory cell.
The disclosure is objected to because of the following informalities:
The following respective paragraphs should be amended as follows to fix grammatical errors or typos:
According to another aspect, a multi-level non-volatile memory device comprises (minimally): at least one non-volatile memory cell configure to be in any one of N levels or states, N being even and greater than two, corresponding respectively to N logical data values (each value being a datum) that can be stored in the memory cell and to N corresponding read current ranges; a read circuit configured to read the datum stored in the memory cell by carrying out successive comparisons of a read current output by the memory cell with reference currents selected from a set of N-1 reference currents having values respectively lying between two different successive ranges, using a dichotomous algorithm starting with the reference current having the median value.
In Fig. 1, the reference DISP denotes a multi-level non-volatile memory device comprising at least one non-volatile memory cell MLB storing a datum having any one of N levels, N being even and greater than two.
These levels correspond respectively to N logical data values that can be stored in the memory cell and to N corresponding read current ranges.
For example, when N is equal to 4, the 4 corresponding logic data values can be respectively equal to 00, 01, 10, and 11 , in binary format.
The device DISP further comprises a circuit for reading the datum stored in the memory cell and configured, as will be seen in more detail hereinbelow, to carry out successive comparisons of a read current Iread output by the memory cell MLB with reference currents Iref selected from a set of N-1 reference currents having values respectively lying between two different successive ranges, using a dichotomous algorithm starting with the reference current having the median value.
As illustrated in Fig. 3, these target values and their associated value range define in this case, for the memory cell MLB, four levels LV0, LV1, LV2 and LV3 respectively corresponding to the following four binary logic values of the datum D: 00, 01, 10, and 11 .
The reading circuit then reads the memory cell MLB (step ST61) by applying a read voltage to the memory cell so as to cause it to output the read current Iread.
If the result Res is equal to 1, the value of A is doubled (step ST72) and, in step ST73, the microcontroller adjusts the reference circuit REF such that it outputs a current Iref, whose value is equal to the previous value increased by N × Imax/A × (N-1) .
If the result Res is equal to 0, the value of A is doubled (step ST75) and, in step ST76, the microcontroller adjusts the reference circuit REF such that it outputs a current Iref, whose value is equal to the previous value decreased by N × Imax/A × (N-1) .
The reading of the cell MLB is a single-input read (as opposed to a differential read) described with reference to Fig. 9.
These two voltages VBL1 and VBL2 are respectively output by the two voltage generators GEN1 and GEN2.
The voltage VBL1 generates a current corresponding to the SET state of the memory cell MLB (typically 12 microamperes).
The voltage VBL2 is less than or equal to the voltage VBL1, in order to cause the selected reference current to be output from [[to]] the reference memory cell CELR.
Thus, as illustrated in Fig. 11, wherein the memory cells are referenced with the group CEL, a row of memory cells includes groups of a plurality of memory cells.
Control circuit MCM, for example a logic circuit, is thus configured to successively select said switches SW so that the reading circuit can successively read each memory cell MLB as explained hereinabove.
In practice, a group Nb of memory cells associated with a single reference memory cell CELR could be selected, for example.
Appropriate correction is required.
Claim Objections
Claims 5, 7, 12, and 14-18 objected to because of the following informalities:
Regarding claim 5: It is suggested to change “the corresponding reference currents” to
“corresponding reference currents” since this is the first reference to such currents.
Regarding claim 7: Stating “programming the multi-level non-volatile memory cell to a level lower than a maximum level comprises” makes is seem that programming the multi-level non-volatile memory cell to a level lower than a maximum level was already mentioned but it wasn’t. Hence, Examiner suggests amending the claim as follows:
The method according to claim 1, wherein the multi-level non-volatile memory cell is a phase-change type memory cell, and the multi-level non-volatile memory cell is programmed to a level lower than a maximum level by programming the multi-level non-volatile memory cell to the maximum level, and then successively outputting erase pulses erasing the multi-level non-volatile memory cell, respectively followed by successively reading the multi-level non-volatile memory cell until a read current corresponding to the desired programming level is reached.
Regarding claim 12: To correct grammar, it is suggested to amend the claim as follows:
The device according to claim 8, wherein the multi-level non-volatile memory cell is a phase-change type memory cell; wherein the phase-change type reference memory cell is programmed in a SET state[[;]], wherein the reading circuit comprises:
a reference memory cell located next to the multi-level non-volatile memory cell and structurally identical to the multi-level non-volatile memory cell; and
a read module configured to perform successive readings of the reference memory cell to cause the reference memory cell to output the corresponding reference currents[[;]] , wherein the read module is configured to apply a selected reference voltage to the reference memory cell to cause it to output the corresponding reference current.
Regarding claim 14: To correct grammar, it is suggested to amend the claim as follows:
The device according to claim 8, wherein the multi-level non-volatile memory cell is a phase-change type memory cell, further comprising:
a processing circuit configured to program the multi-level non-volatile memory cell to the desired level[[; and]],
wherein the reading circuit is configured to check the programming by reading the multi-level non-volatile memory cell[[;]], and
wherein the processing circuit is configured to program the multi-level non-volatile memory cell to a level lower than a maximum level by programming the multi-level non-volatile memory cell to the maximum level, then by successively outputting erase pulses erasing the multi-level non-volatile memory cell, respectively followed by successively reading the multi-level non-volatile memory cell until a read current corresponding to the desired programming level is reached.
Regarding claim 15: To correct grammar, it is suggested to amend the claim as follows:
A method for managing the operation of a multi-level non-volatile memory cell, wherein the multi-level non-volatile memory cell is a phase change type memory cell having N levels, N being greater than or equal to two, corresponding respectively to N logical data likely to be stored in the multi-level non-volatile memory cell and N corresponding read current ranges, the method comprising:
reading the logical data stored in the multi-level non-volatile memory cell with successive comparisons a read current delivered by the multi-level non-volatile memory cell with reference currents chosen from a set of N-1 reference currents having values respectively located between two different successive ranges, wherein the reading uses a dichotomous algorithm starting with the reference current having a median value;
placing, next to the multi-level non-volatile memory cell, a reference memory cell [[a]] of the phase change type and structurally identical to the multi-level non-volatile memory cell; and
successively reading this reference memory cell to cause delivery of corresponding reference currents, wherein delivery of the corresponding reference currents comprises placing the reference memory cell in an initialized state and applying a selected reference voltage to the reference memory cell to cause delivery of the corresponding reference currents[[;]]
.
Regarding claim 16: To correct grammar, it is suggested to amend the claim as follows:
The method of claim 15 further comprising:
programming the multi-level non-volatile memory cell at a desired programming level and verifying programming at the desired level by reading said multi-level non-volatile memory cell.
Regarding claim 17: To correct grammar, it is suggested to amend the claim as follows:
The method of claim 16, wherein said programming comprises programming the multi-level non-volatile memory cell at a desired programming level below a maximum programming level by programming the multi-level non-volatile memory cell at the maximum programming level and then successively delivering erasure pulses to the multi-level non-volatile memory cell respectively followed by successive reads of the multi-level non-volatile memory cell until a read current corresponding to the desired programming level is reached.
Regarding claim 18: To correct grammar, it is suggested to amend the claim as follows:
A multi-level non-volatile memory device, comprising:
at least one multi-level non-volatile memory cell, wherein the multi-level non-volatile memory cell is a phase change type memory cell having N levels, N being greater than or equal to two, corresponding respectively to N logical data likely to be stored in the multi-level non-volatile memory cell and N corresponding read current ranges; and
a circuit for reading data stored in the multi-level non-volatile memory cell, wherein said circuit is configured to perform successive comparisons of a read current delivered by the multi-level non-volatile memory cell with reference currents selected from a set of N-1 reference currents having values respectively located between two different successive ranges, using a dichotomous algorithm starting with the reference current having a median value in which the circuit for reading comprises:
a reference memory cell of phase change type, located next to the multi-level non-volatile memory cell and structurally identical to the multi-level non-volatile memory cell; and
a read module configured to perform successive reads of said reference memory cell to deliver corresponding reference currents, wherein the reference memory cell is programmed in an initialized state and the read module is configured to apply a reference voltage to the reference memory cell to cause delivery of the corresponding reference current[[;]]
.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 6 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The claim refers to “checking the programming by using said reading” but said reading in claim 1 is reading “using a dichotomous algorithm starting with the reference current having the median value”. This was not clearly disclosed in the specification. Although the phrase “checking the programming by using said reading of the memory cel” is found in the specification, it is unclear in each instance to what “said reading” is meant to refer in each instance in the specification. A reading used for such checking or verifying, including outputting a reference current, wherein placing the reference memory cell in a SET state and applying a selected reference voltage to the reference memory cell to cause it to output the corresponding reference current would make sense but a reading “using a dichotomous algorithm starting with the reference current having the median value” for such checking does not seem to make sense since during programing the system already knows what the intended programming state is so the current to be reached is already known and does not need to be searched for, and thus that already known reference current can be immediately used so there would be no need to execute a dichotomous algorithm to search for which state among the possible programming states if any the memory cell may be in after each programming pulse. Pasotti discloses that a dichotomic algorithm is made up of two steps to search for or discover in which section such as an upper half or a lower half of possible program states of that section the memory cell may be in. Such an algorithm is used when we already know for sure that the memory cell has been programmed in one of the program states but we don’t know which one, and is not for checking or verifying if a cell has been successfully programmed to a pre-determined target state for which we already know the current value that needs to be reached.
Hence, the claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1: There is insufficient antecedent basis for this limitation “the datum’ and “the median value” in the claim. Claims 2-7 depend on claim 1.
Regarding claim 8: There is insufficient antecedent basis for this limitation “the median value” in the claim. Claims 9-14 depend on claim 8.
Regarding claim 15: There is insufficient antecedent basis for this limitation “the median value” in the claim. Claims 16-17 depend on claim 15.
Regarding claim 18: There is insufficient antecedent basis for this limitation “the median value” in the claim. Claims 19-20 depend on claim 18.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, and 8-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pasottie et al. (US 2002/0196664A1).
Regarding claim 1: In so far as definite, Pasotti teaches (FIG. 1; [0024-0050]) a method for managing operation of a multi-level non-volatile memory cell (MC1 or MC2 in FIG. 1), the multi-level non-volatile memory cell having N levels (each cell stores any one of N values, each value having 2 bits or 4 bits; see [0005, 0032, 0047]), N being even and greater than two (2 bits/cell means there are four values and 4 bits/cell means there are sixteen values), corresponding respectively to N logical data that can be stored in the multi-level non-volatile memory cell and to N corresponding read current ranges ([0047]), the method comprising:
reading the datum [a datum] (a value corresponding to 2 or 4 bits that are stored in a memory cell) stored in the multi-level non-volatile memory cell by performing successive comparisons of a read current output by the multi-level non-volatile memory cell with reference currents selected from a set of N-1 reference currents having values respectively lying between two different successive ranges using a dichotomous algorithm starting with the reference current having the median value ([0035-0036, 0043-0050]; to perform the disclosed discriminating of whether the memory cell current is one of two possible values each step of the dichotomic algorithm, it is inherent that the reference current has a value lying between the two ranges/values).
Regarding claim 2: Pasotti (FIG. 1; [0024-0050]) teaches the method according to claim 1, wherein a reference memory cell (RC1 in FIG. 1) that is structurally identical to the multi-level non-volatile memory cell (RC1 is identical to MC1 in that it is a floating-gate transistor type memory cell; the same transistor circuit symbol is used) is placed next to the multi-level non-volatile memory cell (RC1 is seen to be arranged in an adjacent column of a memory cell array, and MC1 an RC1 are coupled to the same word line WL1), and wherein reading comprises successively reading the reference memory cell to cause the reference memory cell to output the corresponding reference currents from the set of N-1 reference currents (Pasotti discloses using a dichotomic algorithm in [0043-0050], wherein in two steps, for example, comparator 14 performs a comparison of a memory cell current with a respective reference current in each step, and varies the reference current by using successive approximation register 15 to change a mirroring ratio; [0025-0051]).
Regarding claim 3: Pasottie teaches the method according to claim 1, wherein reading comprises successively adjusting an adjustable current source (“a variable reference current generator”; see [0050]) to cause the adjustable current source to output the corresponding reference currents from the set of N-1 reference currents ([0047] discloses that when there are 4 programmed states then 3 reference currents corresponding to three different current mirroring factors are needed; hence N-1 reference currents are needed when there are N values or program states).
Regarding claim 8: In so far as definite, Pasotti teaches (FIG. 1; [0024-0050]) a multi-level non-volatile memory device, comprising:
at least one non-volatile memory cell (MC1 or MC2 in FIG. 1) having N levels (each cell stores any one of N values, each value having 2 bits or 4 bits; see [0005, 0032, 0047]), N being even and greater than two (2 bits/cell means there are four values and 4 bits/cell means there are sixteen values), corresponding respectively to N logical data that can be stored in the multi-level non-volatile memory cell and to N corresponding read current ranges ([0047]); and
a reading circuit (the circuitry in FIG. 1 except for the memory cells and the reference cells) configured to read a datum stored in the multi-level non-volatile memory cell (a value corresponding to the number of bits and the bit values that are stored in the memory cell) by carrying out successive comparisons of a read current output by the multi-level non-volatile memory cell with reference currents selected from a set of N-1 reference currents having values respectively lying between two different successive ranges using a dichotomous algorithm starting with the reference current having the median value ([0035-0036, 0043-0050]; to perform the disclosed discriminating of whether the memory cell current is one of two possible values each step of the dichotomic algorithm, it is inherent that the reference current has a value lying between the two ranges/values).
Regarding claim 9: Pasotti (FIG. 1; [0024-0050]) teaches the device according to claim 8, wherein the reading circuit comprises: a reference memory cell (RC1 in FIG. 1) located next to the multi-level non-volatile memory cell and structurally identical to the multi-level non-volatile memory cell (RC1 is identical to MC1 in that it is a floating-gate transistor type memory cell; the same transistor circuit symbol is used); and a read module (the circuitry in FIG. 1 except for the array of memory cells) configured to perform successive readings of the reference memory cell to cause the reference memory cell to output the corresponding reference currents (Pasotti discloses using a dichotomic algorithm in [0043-0050], wherein in two steps, for example, comparator 14 performs a comparison of a memory cell current with a respective reference current in each step, and varies the reference current by using successive approximation register 15 to change a mirroring ratio; [0025-0051]).
Regarding claim 10: Pasotti teaches the device according to claim 8, wherein the reading circuit comprises: an adjustable current source (“a variable reference current generator”; see [0050]); and a control circuit (successive approximation register 15) configured to make successive adjustments to the current source to cause it to output successively selected reference currents ([0047-0050]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4, 11, 15 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pasotti et al. (US 2002/0196664 A1) in view of Hoenigschmid (US 2008/0170444 A1).
Regarding claim 4: Pasotti does not specifically teach the method according to claim 1, wherein the multi-level non-volatile memory cell is a phase-change type memory cell.
Hoenigschmid ([0007-0012]) teaches a multi-level phase change memory cell being an alternative to a multi-level floating gate type memory cell.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Hoenigschmid into the device and/or method of Pasotti in a manner such that each of the memory cells and the reference cells would be phase change type like that taught by Hoenigschmid; thus the reference memory cell would be a phase change memory cell structurally identical to the multi-level non-volatile memory cell (material structure is disclosed in [0007] of Hoenigschmid). The motivation to do would have been to use an alternative type of multi-level memory cell as exemplified by Hoenigschmid in place of the floating-gate transistor type of multi-level memory cell such that, like that of the floating gate type of memory cell, the strength of the electrical current depends on the state of the memory cell and the memory cell is read by comparing an electrical quantity with a reference quantity ([0008] of Hoenigschmid).
Regarding claim 11: Pasotti does not specifically teach the multi-level non-volatile memory cell is a phase-change type memory cell.
Hoenigschmid ([0007-0012]) teaches a multi-level phase change memory cell being an alternative to a multi-level floating gate type memory cell.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Hoenigschmid into the device and/or method of Pasotti in a manner such that each of the memory cells and the reference cells would be phase change type like that taught by Hoenigschmid; thus the reference memory cell would be a phase change memory cell structurally identical to the multi-level non-volatile memory cell (material structure is disclosed in [0007] of Hoenigschmid). The motivation to do would have been to use an alternative type of multi-level memory cell as exemplified by Hoenigschmid in place of the floating-gate transistor type of multi-level memory cell such that, like that of the floating gate type of memory cell, the strength of the electrical current depends on the state of the memory cell and the memory cell is read by comparing an electrical quantity with a reference quantity ([0008] of Hoenigschmid).
Regarding claim 15: In so far as definite, Pasotti teaches (FIG. 1; [0024-0050]) a method for managing the operation of a multi-level non-volatile memory cell (MC1 or MC2 in FIG. 1), wherein the multi-level non-volatile memory cell has N levels (each cell stores any one of N values, each value having 1 bit or 2 bits or 4 bits; see [0005, 0032, 0047]), N being greater than or equal to two (1 bit can have any one of 2 values, 2 bits/cell means there are four values and 4 bits/cell means there are sixteen values; a value maps to Applicant’s level), corresponding respectively to N logical data likely to be stored in the multi-level non-volatile memory cell and N corresponding read current ranges ([0047]), the method comprising:
reading the logical data stored in the multi-level non-volatile memory cell with successive comparisons a read current delivered by the multi-level non-volatile memory cell with reference currents chosen from a set of N-1 reference currents having values respectively located between two different successive ranges ([0035-0036, 0043-0050]; to perform the disclosed discriminating of whether the memory cell current is one of two possible values each step of the dichotomic algorithm, it is inherent that the reference current has a value lying between the two ranges/values);
wherein reading uses a dichotomous algorithm starting with the reference current having the median value ([0048-0049]);
placing, next to the multi-level non-volatile memory cell (MC1), a reference memory cell (RC1) structurally identical to the multi-level non-volatile memory cell; and
successively reading this reference memory cell to cause delivery of corresponding reference currents ([0048-0049]);
wherein delivery of a reference current comprises placing the reference memory cell in an initialized state ([0043]) and applying a selected reference voltage (VG; [0039]) to the reference memory cell to cause delivery of the corresponding reference current.
Pasotti does not specifically teach the following:
the multi-level non-volatile memory cell is a phase change type memory cell; and
the reference memory cell is a phase change memory cell structurally identical to the multi-level non-volatile memory cell.
Hoenigschmid ([0007-0012]) teaches a multi-level phase change memory cell being an alternative to a multi-level floating gate type memory cell.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Hoenigschmid into the device and/or method of Pasotti in a manner such that each of the memory cells and the reference cells would be phase change type like that taught by Hoenigschmid; thus the reference memory cell would be a phase change memory cell structurally identical to the multi-level non-volatile memory cell (material structure is disclosed in [0007] of Hoenigschmid). The motivation to do would have been to use an alternative type of multi-level memory cell as exemplified by Hoenigschmid in place of the floating-gate transistor type of multi-level memory cell such that, like that of the floating gate type of memory cell, the strength of the electrical current depends on the state of the memory cell and the memory cell is read by comparing an electrical quantity with a reference quantity ([0008] of Hoenigschmid).
Regarding claim 18: In so far as definite, Pasotti teaches (FIG. 1; [0024-0050]) a multi-level non-volatile memory device, comprising:
at least one multi-level non-volatile memory cell (MC1 or MC2 in FIG. 1);
wherein the multi-level non-volatile memory cell is a memory cell having N levels (each cell stores any one of N values, each value having 1 bit or 2 bits or 4 bits; see [0005, 0032, 0047]), N being greater than or equal to two (1 bit can have any one of 2 values, 2 bits/cell means there are four values and 4 bits/cell means there are sixteen values; a value maps to Applicant’s level), corresponding respectively to N logical data likely to be stored in the multi-level non-volatile memory cell and N corresponding read current ranges ([0047]);
a circuit (the circuitry in FIG. 1 except for the memory cells and the reference cells) for reading data stored in the multi-level non-volatile memory cell, wherein said circuit is configured to perform successive comparisons of a read current delivered by the multi-level non-volatile memory cell with reference currents selected from a set of N-1 reference currents having values respectively located between two different successive ranges ([0035-0036, 0043-0050]; to perform the disclosed discriminating of whether the memory cell current is one of two possible values each step of the dichotomic algorithm, it is inherent that the reference current has a value lying between the two ranges/values), using a dichotomous algorithm ([0048-0049]) starting with the reference current having the median value in which the circuit for reading comprises:
a reference memory cell (RC1), located next to the multi-level non-volatile memory cell (MC1) and structurally identical to the multi-level non-volatile memory cell (each is a floating-gate transistor); and
a read module (the circuitry in FIG. 1 except for the memory cells and the reference cells) configured to perform successive reads of said reference memory cell to deliver corresponding reference currents ([0035-0036, 0043-0050]; to perform the disclosed discriminating of whether the memory cell current is one of two possible values each step of the dichotomic algorithm, it is inherent that the reference current has a value lying between the two ranges/values);
wherein the reference memory cell is programmed in an initialized state ([0043]) and the read module is configured to apply a reference voltage (VG; [0039]) to the reference memory cell to cause delivery of the corresponding reference current.
Pasotti does not specifically teach the following:
the multi-level non-volatile memory cell is a phase change type memory cell; and
the reference memory cell is a phase change memory cell structurally identical to the multi-level non-volatile memory cell.
Hoenigschmid ([0007-0012]) teaches a multi-level phase change memory cell being an alternative to a multi-level floating gate type memory cell.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Hoenigschmid into the device and/or method of Pasotti in a manner such that each of the memory cells and the reference cells would be phase change type like that taught by Hoenigschmid; thus the reference memory cell would be a phase change memory cell structurally identical to the multi-level non-volatile memory cell (material structure is disclosed in [0007] of Hoenigschmid). The motivation to do would have been to use an alternative type of multi-level memory cell as exemplified by Hoenigschmid in place of the floating-gate transistor type of multi-level memory cell such that, like that of the floating gate type of memory cell, the strength of the electrical current depends on the state of the memory cell and the memory cell is read by comparing an electrical quantity with a reference quantity ([0008] of Hoenigschmid).
Claim(s) 5 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pasotti (US 2002/0196664 A1) in view of Hoenigschmid (US 2008/0170444 A1) and Pasotti et al. (US 2020/0135273 A1; hereinafter “Pasotti_273”).
Regarding claim 5: Pasottii (FIG. 1; [0024-0050]) teaches the method according to claim 1, wherein a reference memory cell (RC1) that is structurally identical to the multi-level non-volatile memory cell (RC1 is identical to MC1 in that it is a floating-gate transistor type memory cell; the same transistor circuit symbol is used) is placed next to the multi-level non-volatile memory cell (RC1 is seen to be arranged in an adjacent column of a memory cell array, and MC1 an RC1 are coupled to the same word line WL1), wherein reading comprises successively reading the reference memory cell to cause the reference memory cell to output the corresponding reference currents from the set of N-1 reference currents (Pasotti discloses using a dichotomic algorithm in [0043-0050], wherein in two steps, for example, comparator 14 performs a comparison of a memory cell current with a respective reference current in each step, and varies the reference current by using successive approximation register 15 to change a mirroring ratio; [0025-0051]), and further comprising: and applying a selected reference voltage to the reference memory cell to cause it to output the corresponding reference current (VG is applied to the word line; [0039]; also see FIG. 1).
Pasotti does not specifically teach:
the multi-level non-volatile memory cell is a phase-change type memory cell; and
the reference memory cell is a phase-change memory cell
Hoenigschmid ([0007-0012]) teaches a multi-level phase change memory cell being an alternative to a multi-level floating gate type memory cell.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Hoenigschmid into the device and/or method of Pasotti in a manner such that each of the memory cells and the reference cells would be phase change type like that taught by Hoenigschmid; thus the reference memory cell would be a phase change memory cell structurally identical to the multi-level non-volatile memory cell (material structure is disclosed in [0007] of Hoenigschmid). The motivation to do would have been to use an alternative type of multi-level memory cell as exemplified by Hoenigschmid in place of the floating-gate transistor type of multi-level memory cell such that, like that of the floating gate type of memory cell, the strength of the electrical current depends on the state of the memory cell and the memory cell is read by comparing an electrical quantity with a reference quantity ([0008] of Hoenigschmid).
Pasotti teaches in [0043] that the memory cell RC1, for example, is programmed in a predetermined condition but Pasotti as modified above does not specifically teach placing the reference memory cell in a SET state.
Pasotti_273 (FIG. 1; [0030-0036]) teaches a phase change memory comprising phase change memory cells and phase change reference cells, wherein a phase change memory reference cell in a SET state in a variable current generator is used to generate a reference current for comparison in a reading operation.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Pasotti_273 in the device and/or method of Pasotti as modified above in a manner such that each reference memory would be in a SET state since Pasotti_273 discloses that such a reference cell in such a state is suitable for effectively tracking the resistance drift of memory cells, and the tracking effect is more pronounced for the cells in the SET state ([0033-0035] of Pasotti_273).
Regarding claim 12: Pasottii (FIG. 1; [0024-0050]) teaches the device, wherein the reading circuit comprises: a reference memory cell (RC1) located next to the multi-level non-volatile memory cell (RC1 is seen to be arranged in an adjacent column of a memory cell array, and MC1 an RC1 are coupled to the same word line WL1) and structurally identical to the multi-level non-volatile memory cell (RC1 is identical to MC1 in that it is a floating-gate transistor type memory cell; the same transistor circuit symbol is used); and a read module (circuitry in FIG. 1 except for the memory cell array) configured to perform successive readings of the reference memory cell to cause the reference memory cell to output the corresponding reference currents (Pasotti discloses using a dichotomic algorithm in [0043-0050], wherein in two steps, for example, comparator 14 performs a comparison of a memory cell current with a respective reference current in each step, and varies the reference current by using successive approximation register 15 to change a mirroring ratio; [0025-0051]); and wherein the read module is configured to apply a selected reference voltage to the reference memory cell to cause it to output the corresponding reference current (VG is applied to the word line; [0039]; also see FIG. 1).
Pasotti does not specifically teach:
the multi-level non-volatile memory cell is a phase-change type memory cell; and
the reference memory cell is a phase-change memory cell
Hoenigschmid ([0007-0012]) teaches a multi-level phase change memory cell being an alternative to a multi-level floating gate type memory cell.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Hoenigschmid into the device and/or method of Pasotti in a manner such that each of the memory cells and the reference cells would be phase change type like that taught by Hoenigschmid; thus the reference memory cell would be a phase change memory cell structurally identical to the multi-level non-volatile memory cell (material structure is disclosed in [0007] of Hoenigschmid). The motivation to do would have been to use an alternative type of multi-level memory cell as exemplified by Hoenigschmid in place of the floating-gate transistor type of multi-level memory cell such that, like that of the floating gate type of memory cell, the strength of the electrical current depends on the state of the memory cell and the memory cell is read by comparing an electrical quantity with a reference quantity ([0008] of Hoenigschmid).
Pasotti teaches in [0043] that the memory cell RC1, for example, is programmed in a predetermined condition but Pasotti as modified above does not specifically teach placing the reference memory cell in a SET state.
Pasotti_273 (FIG. 1; [0030-0036]) teaches a phase change memory comprising phase change memory cells and phase change reference cells, wherein a phase change memory reference cell in a SET state in a variable current generator is used to generate a reference current for comparison in a reading operation.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Pasotti_273 in the device and/or method of Pasotti as modified above in a manner such that each reference memory would be in a SET state since Pasotti_273 discloses that such a reference cell in such a state is suitable for effectively tracking the resistance drift of memory cells, and the tracking effect is more pronounced for the cells in the SET state ([0033-0035] of Pasotti_273).
Claim(s) 16-17 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pasotti (US 2002/0196664 A1) as modified by Hoenigschmid (US 2008/0170444 A1), and further in view of Vianello et al. (US 2021/0035638 A1).
Regarding claims 16-17: Pasotti as modified by Hoenigschmid does not specifically teach the method of claim 15 further comprising:
programming the multi-level non-volatile memory cell at a desired programming level and verifying programming at the desired level [by] reading said multi-level non-volatile memory cell, wherein programming comprises programming the multi-level non-volatile memory cell at a desired programming level below a maximum programming level by programming the multi-level non-volatile memory cell at the maximum programming level and then successively delivering erasure pulses to the multi-level non-volatile memory cell respectively followed by successive reads of the multi-level non-volatile memory cell until a read current corresponding to the desired programming level is reached.
Vianello teaches programming a resistive type multi-level non-volatile memory cell at a desired programming level and verifying programming at the desired level by reading said multi-level non-volatile memory cell ([0003]; FIG. 4; [0059,0082-0085] and FIG. 7; [0099-0115]). Also, teaches that the initial state of a memory cell before programming may be either the highest or lowest resistive state ([0101-0105]) so that each pulse may consecutively reduce or increase the resistance depending on the initial state of the memory cell until a read current corresponding to the desired programming level is reached.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Vianello into the device and/or method of Pasotti as modified by Hoenigschmid in a manner such that there would be a programming of the multi-level non-volatile memory cell at a desired programming level and there would be verifying the programming at the desired level by reading said multi-level non-volatile memory cell in a manner similar to that taught by Vianello, wherein either consecutive RESET pulses or SET pulses would be applied depending on if the initial state is in the lowest resistance state or in the highest resistance state, with reading performed between the pulses. Hence, there would be programming of the multi-level non-volatile memory cell at a desired programming level and verifying programming at the desired level by reading said multi-level non-volatile memory cell, wherein programming would comprise programming the multi-level non-volatile memory cell at a desired programming level below a maximum programming level by programming the multi-level non-volatile memory cell at the maximum programming level by using pulses that increase the resistance and then successively delivering erasure pulses, pulses that decrease the resistance, to the multi-level non-volatile memory cell respectively followed by successive reads of the multi-level non-volatile memory cell until a read current corresponding to the desired programming level is reached. The motivation to do so would be to use an already known programming technique suitable for programming resistive type memory cells as exemplified by Vianello.
Regarding claims 19-20: Pasotti as modified by Hoenigschmid does not specifically teach the apparatus of claim 18, further comprising a processing circuit configured to perform a programming of the multi-level non-volatile memory cell at a desired programming level and to perform a programming check by reading said multi-level non-volatile memory cell, wherein the processing circuit is configured to perform memory cell programming at a desired programming level below a maximum programming level by programming the multi-level non-volatile memory cell at the maximum programming level and then performing successive deliveries of memory cell erasure pulses respectively followed by successive reads from the multi-level non-volatile memory cell until reaching a read current corresponding to the desired programming level.
Vianello teaches programming a resistive type multi-level non-volatile memory cell at a desired programming level and verifying programming at the desired level by reading said multi-level non-volatile memory cell ([0003]; FIG. 4; [0059,0082-0085] and FIG. 7; [0099-0115]). Also, teaches that the initial state of a memory cell before programming may be either the highest or lowest resistive state ([0101-0105]) so that each pulse may consecutively reduce or increase the resistance depending on the initial state of the memory cell until a read current corresponding to the desired programming level is reached.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Vianello into the device and/or method of Pasotti as modified by Hoenigschmid in a manner such that there would be a programming of the multi-level non-volatile memory cell at a desired programming level and there would be verifying the programming at the desired level by reading said multi-level non-volatile memory cell in a manner similar to that taught by Vianello, wherein either consecutive RESET pulses or SET pulses would be applied depending on if the initial state is in the lowest resistance state or in the highest resistance state, with reading performed between the pulses. Hence, the apparatus would further comprise a processing circuit configured to perform a programming of the multi-level non-volatile memory cell at a desired programming level and to perform a programming check by reading said multi-level non-volatile memory cell, wherein the processing circuit is configured to perform memory cell programming at a desired programming level below a maximum programming level by programming the multi-level non-volatile memory cell at the maximum programming level and then performing successive deliveries of memory cell erasure pulses respectively followed by successive reads from the multi-level non-volatile memory cell until reaching a read current corresponding to the desired programming level. The motivation to do so would be to use an already known programming technique suitable for programming resistive type memory cells as exemplified by Vianello.
Claim(s) 7 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pasotti (US 2002/0196664 A1) in view of Hoenigschmid (US 2008/0170444 A1) and Vianello et al. (US 2021/0035638 A1).
Regarding claim 7: Pasotti does not specifically teach the method according to claim 1, wherein the multi-level non-volatile memory cell is a phase-change type memory cell.
Hoenigschmid ([0007-0012]) teaches a multi-level phase change memory cell being an alternative to a multi-level floating gate type memory cell.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Hoenigschmid into the device and/or method of Pasotti in a manner such that each of the memory cells and the reference cells would be phase change type like that taught by Hoenigschmid; thus the reference memory cell would be a phase change memory cell structurally identical to the multi-level non-volatile memory cell (material structure is disclosed in [0007] of Hoenigschmid). The motivation to do would have been to use an alternative type of multi-level memory cell as exemplified by Hoenigschmid in place of the floating-gate transistor type of multi-level memory cell such that, like that of the floating gate type of memory cell, the strength of the electrical current depends on the state of the memory cell and the memory cell is read by comparing an electrical quantity with a reference quantity ([0008] of Hoenigschmid).
Pasottie as modified above does not specifically teach programming the multi-level non-volatile memory cell to a level lower than a maximum level, wherein the multi-level non-volatile memory cell is programmed to the maximum level, and then successively outputting erase pulses erasing the multi-level non-volatile memory cell, respectively followed by successively reading the multi-level non-volatile memory cell until a read current corresponding to the desired programming level is reached.
Vianello teaches programming a resistive type multi-level non-volatile memory cell at a desired programming level and verifying programming at the desired level by reading said multi-level non-volatile memory cell ([0003]; FIG. 4; [0059,0082-0085] and FIG. 7; [0099-0115]). Also, teaches that the initial state of a memory cell before programming may be either the highest or lowest resistive state ([0101-0105]) so that each pulse may consecutively reduce or increase the resistance depending on the initial state of the memory cell until a read current corresponding to the desired programming level is reached.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Vianello into the device and/or method of Pasotti as modified by Hoenigschmid in a manner such that there would be a programming of the multi-level non-volatile memory cell at a desired programming level and there would be verifying the programming at the desired level by reading said multi-level non-volatile memory cell in a manner similar to that taught by Vianello, wherein either consecutive RESET pulses or SET pulses would be applied depending on if the initial state is in the lowest resistance state or in the highest resistance state, with reading performed between the pulses. Hence, the apparatus would further comprise a processing circuit configured to perform a programming of the multi-level non-volatile memory cell at a desired programming level and to perform a programming check by reading said multi-level non-volatile memory cell, wherein the processing circuit is configured to perform memory cell programming at a desired programming level below a maximum programming level by programming the multi-level non-volatile memory cell at the maximum programming level and then performing successive deliveries of memory cell erasure pulses respectively followed by successive reads from the multi-level non-volatile memory cell until reaching a read current corresponding to the desired programming level. The motivation to do so would be to use an already known programming technique suitable for programming resistive type memory cells as exemplified by Vianello.
Regarding claim 14: Pasotti does not specifically teach the method according to claim 1, wherein the multi-level non-volatile memory cell is a phase-change type memory cell.
Hoenigschmid ([0007-0012]) teaches a multi-level phase change memory cell being an alternative to a multi-level floating gate type memory cell.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Hoenigschmid into the device and/or method of Pasotti in a manner such that each of the memory cells and the reference cells would be phase change type like that taught by Hoenigschmid; thus the reference memory cell would be a phase change memory cell structurally identical to the multi-level non-volatile memory cell (material structure is disclosed in [0007] of Hoenigschmid). The motivation to do would have been to use an alternative type of multi-level memory cell as exemplified by Hoenigschmid in place of the floating-gate transistor type of multi-level memory cell such that, like that of the floating gate type of memory cell, the strength of the electrical current depends on the state of the memory cell and the memory cell is read by comparing an electrical quantity with a reference quantity ([0008] of Hoenigschmid).
Pasottie as modified above does not specifically teach a processing circuit configured to program the multi-level non-volatile memory cell to the desired level; and wherein the reading circuit is configured to check the programming by reading the multi-level non-volatile memory cell; and wherein the processing circuit is configured to program the multi-level non-volatile memory cell to a level lower than a maximum level by programming the multi-level non-volatile memory cell to the maximum level, then by successively outputting erase pulses erasing the multi-level non-volatile memory cell, respectively followed by successively reading the multi-level non-volatile memory cell until a read current corresponding to the desired programming level is reached.
Vianello teaches programming a resistive type multi-level non-volatile memory cell at a desired programming level and verifying programming at the desired level by reading said multi-level non-volatile memory cell ([0003]; FIG. 4; [0059,0082-0085] and FIG. 7; [0099-0115]). Also, teaches that the initial state of a memory cell before programming may be either the highest or lowest resistive state ([0101-0105]) so that each pulse may consecutively reduce or increase the resistance depending on the initial state of the memory cell until a read current corresponding to the desired programming level is reached.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Vianello into the device and/or method of Pasotti as modified by Hoenigschmid in a manner such that there would be a programming of the multi-level non-volatile memory cell at a desired programming level and there would be verifying the programming at the desired level by reading said multi-level non-volatile memory cell in a manner similar to that taught by Vianello, wherein either consecutive RESET pulses or SET pulses would be applied depending on if the initial state is in the lowest resistance state or in the highest resistance state, with reading performed between the pulses. Hence, the apparatus would further comprise a processing circuit configured to perform a programming of the multi-level non-volatile memory cell at a desired programming level and to perform a programming check by reading said multi-level non-volatile memory cell, wherein the processing circuit is configured to perform memory cell programming at a desired programming level below a maximum programming level by programming the multi-level non-volatile memory cell at the maximum programming level and then performing successive deliveries of memory cell erasure pulses respectively followed by successive reads from the multi-level non-volatile memory cell until reaching a read current corresponding to the desired programming level. The motivation to do so would be to use an already known programming technique suitable for programming resistive type memory cells as exemplified by Vianello.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pasotti (US 2002/0196664 A1) in view of Kim et al. (US 2009/0168493 A1).
Regarding claim 13: Pasotti does not specifically teach the device according to claim 8, further comprising: a processing circuit configured to program the multi-level non-volatile memory cell to the desired level; and wherein the reading circuit is configured to check the programming by reading the multi-level non-volatile memory cell.
Kim (FIG. 10; [0169]) teaches a memory controller (1120 in FIG. 14; [0175]) that controls operation of a memory device that uses an incremental program pulse to program a non-volatile memory cell such as a floating gate type memory transistor or a phase change memory cell, wherein a verify check is performed between program pulses, and once the verify read operation verifies that data has been properly written, the program loop ends, and the write operation ends. Such a method is well known in the art as Incremental Step Pulse Programming (ISPP). Kim (FIG. 18; and [0154]) also teaches using reference cells to read stored data.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kim into the device and/or method of Pasotti in a manner such that a processing circuit would be configured to program the multi-level non-volatile memory cell to the desired level; and wherein the reading circuit would be configured to check the programming by reading the multi-level non-volatile memory cell by controlling 15 of Pasotti to set a the mirroring ration to generate a reference current corresponding to the target programming state The motivation to do would have been to use a an already known technique in the art suitable for programming a non-volatile memory cell such as a floating-gate transistor as exemplified by Kim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827