DETAILED ACTION
Election/Restrictions
Applicant's election with traverse of Species I, FIG. 3 (claims 1-20) in the reply filed on 7/31/26 is acknowledged. The traversal is on the ground(s) that FIG. 1 and 2 are generic and dividing FIG. 3-8 to different Species seems to be improper. Even though the Examiner does not completely concur, all claims (i.e. claims 1-20, no claims currently withdrawn) are being examined. The requirement is still deemed proper, and therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, and 4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Okada US 2011/0175143 A1. Okada discloses (see, for example, FIG. 4, and 3) a semiconductor package 20 comprising: a substrate 2 including a plurality of connection pads 23B; a first semiconductor chip 21A on the substrate 2 and including a plurality of first data pads 24M on an upper surface thereof; a second semiconductor chip 21E on the first semiconductor chip 21A and including a plurality of second data pads on an upper surface thereof; a third semiconductor chip 21F on the second semiconductor chip 21E and including a plurality of third data pads on an upper surface thereof; and a plurality of connection members 25A/25E/25F connecting some of the plurality of connection pads 23B and some of the plurality of first data pads 24M, connecting the plurality of connection pads 23B and the plurality of second data pads, and connecting some of the plurality of second data pads and some of the plurality of third data pads. In paragraph [0039], Okada discloses the pads 24A-24P being alongside the chips 21A-21P.
Regarding claim 2, see, for example, FIG. 4 wherein Okada discloses the second
semiconductor chip 21E is spaced apart from the first semiconductor chip 21A in a vertical direction, and the third semiconductor chip 21F is offset from the second semiconductor chip 21E in a horizontal direction.
Regarding claim 4, see, for example, FIG. 3, and paragraph [0039] wherein Okada
discloses the first semiconductor chip 21A, the second semiconductor chip 21E, and the third semiconductor chip 21F may include NAND memory chips, which have auxiliary pads, and some of the plurality of auxiliary pads of each of the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are command/address pads, which are connected to a controller chip 7, which selects memory chips for programming and reading. Further, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F. 2d 1647 (1987).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 5 thru 8, and 11 thru 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okada US 2011/0175143 A1 as applied to claims 1, 2, and 4 and above, and further in view of Keeth US 2023/0063029 A1. Okada does not specifically disclose the first semiconductor chip and the third semiconductor chip each include an X8-bit structure, respectively, and a second semiconductor chip includes an X16-bit structure. However, Keeth discloses (see, for example, FIG. 3) a semiconductor package 330 that includes a stack of memory dies 305. In paragraph [0050-0051] Keeth discloses memory channels including X8 and X16 that support multiple channel widths. Further, it was well known in the art to have different bit structures including X8 and X16 in memory chips in order to manage space, and/or need for transferring greater amounts of data according to the preferences of the user as a matter of obvious design choice. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the first semiconductor chip and the third semiconductor chip each include an X8-bit structure, respectively, and a second semiconductor chip includes an X16-bit structure in order to manage space, and/or need to for transferring greater amounts of data according to the preferences of the user as a matter of obvious design choice.
Regarding claim 5, Okada does not clearly disclose a buffer chip; however, Keeth
discloses (see, for example, paragraph [0099]) the use of a buffer layer in a memory device. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a buffer layer in order to help drive signals between the dies in the memory stack.
Regarding claim 6, see, for example, FIG. 4, and 3 wherein Okada discloses a
semiconductor package 20 comprising: a substrate 2 including a plurality of connection pads 23B; a first semiconductor chip 21A on the substrate 2 and including a plurality of first data pads 24M on an upper surface thereof; a second semiconductor chip 21E on the first semiconductor chip 21A and including a plurality of second data pads on an upper surface thereof; a third semiconductor chip 21F on the second semiconductor chip 21E and including a plurality of third data pads on an upper surface thereof; a plurality of first connection members 25A connecting the substrate 2 and the first semiconductor chip 21A via the plurality of connection pads 23B and the plurality of first data pads 24M; a plurality of second connection members 25E connecting the substrate 2 and the second semiconductor chip 21E via the plurality of connection pads 23B and the plurality of second data pads; and a plurality of third connection members 25F connecting the third semiconductor chip 21F and the second semiconductor chip 21E via the plurality of second data pads and the plurality of third data pads. In paragraph [0039], Okada discloses the pads 24A-24P being alongside the chips 21A-21P. Regarding the limitation “X8-bit and X16-bit connection architecture”, see the rejection for claim 3 above.
Regarding claim 7, see, for example, FIG. 3 wherein Okada discloses connection members 25 being connected to pads 24. Okada does not specifically disclose the plurality of first connection members are connected to eight first data pads of the plurality of first data pads, the plurality of second connection members are connected to sixteen second data pads of the plurality of second data pads, and the plurality of third connection members are connected to eight third data pads of the plurality of third data pads; however, it would have been obvious to one of ordinary skill in the art to have the plurality of first connection members are connected to eight first data pads of the plurality of first data pads, the plurality of second connection members are connected to sixteen second data pads of the plurality of second data pads, and the plurality of third connection members are connected to eight third data pads of the plurality of third data pads, at a time prior to the effective filing date, in order to manage space and control the amount of bits (i.e. 8 bits or 16 bits) transferred according to the preferences of the user as a matter of obvious design choice.
Regarding claim 8, see, for example, FIG. 4 wherein Okada discloses the second semiconductor chip 21E is spaced apart from the first semiconductor chip 21A in a vertical direction by a fourth semiconductor chip 21C offset from the second semiconductor chip 21E in a horizontal direction, and the third semiconductor chip 21F is offset from the second semiconductor chip 21E in the horizontal direction.
Regarding claims 11, and 18, see, for example, FIG. 3, and paragraph [0039] wherein
Okada discloses the first semiconductor chip 21A, the second semiconductor chip 21E, and the third semiconductor chip 21F may include NAND memory chips, which have auxiliary pads, and some of the plurality of auxiliary pads of each of the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are command/address pads, which are connected to a controller chip 7, which selects memory chips for programming and reading. Further, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F. 2d 1647 (1987).
Regarding claim 12, see, for example, FIG. 4, and 3 wherein Okada discloses a
semiconductor package 20 comprising: a substrate 2 including a plurality of first connection pads 23B and a plurality of second connection pads 23A; a first semiconductor chip 21A on the substrate 2 and disposed between the plurality of first connection pads 23B and the plurality of second connection pads 23A, the first semiconductor chip 21A, and the first semiconductor chip 21A including a plurality of first data pads 24M on an upper surface thereof; a second semiconductor chip 21E on the first semiconductor chip 21A, the second semiconductor chip 21E, and the second semiconductor chip 21E including a plurality of second data pads on an upper surface thereof; a third semiconductor chip 21F on the second semiconductor chip 21E, the third semiconductor chip 21F, and the third semiconductor chip 21F including a plurality of third data pads on an upper surface thereof; a fourth semiconductor chip 21C disposed between the first semiconductor chip 21A and the second semiconductor chip 21E, the fourth semiconductor chip 21C, and the fourth semiconductor chip 21C including a plurality of fourth data pads on an upper surface thereof; a fifth semiconductor chip 21G on the third semiconductor chip 21F, the fifth semiconductor chip 21G, and the fifth semiconductor chip 21G including a plurality of fifth data pads on an upper surface thereof; a sixth semiconductor chip 21H on the fifth semiconductor chip 21G, the sixth semiconductor chip 21H, and the sixth semiconductor chip 21H including a plurality of sixth data pads on an upper surface thereof; a plurality of first connection members 25A connecting some of the plurality of first connection pads 23B and some of the plurality of first data pads 24M; a plurality of second connection members 25E connecting the plurality of first connection pads 23B and the plurality of second data pads; a plurality of third connection members 225F connecting some of the plurality of second data pads and some of the plurality of third data pads; a plurality of fourth connection members 25C connecting some of the plurality of second connection pads 23A and some of the plurality of fourth data pads; a plurality of fifth connection members 25G connecting the plurality of second connection pads 23A and the plurality of fifth data pads; and a plurality of sixth connection members 25H connecting some of the plurality of fifth data pads and some of the plurality of sixth data pads. In paragraph [0039], Okada discloses the pads 24A-24P being alongside the chips 21A-21P. Regarding the limitation “X8-bit and X16-bit structure”, see the rejection for claim 3 above.
Regarding claim 13, see, for example, FIG. 4, and 3 wherein Okada discloses the plurality of first connection pads 23B are disposed at a first side of the first semiconductor chip 21A, and the plurality of second connection pads 23A are disposed at a second side that is opposite to the first side of the first semiconductor chip 21A.
Regarding claim 14, see, for example, FIG. 4, and 3 wherein Okada discloses the fourth semiconductor chip 21C is stacked on the first semiconductor chip 21A and offset to expose the plurality of first data pads 24M.
Regarding claim 15, see, for example, FIG. 4 wherein Okada discloses the second semiconductor chip 21E is stacked on the fourth semiconductor chip 21C to fully overlap the first semiconductor chip 21A in a plan view.
Regarding claim 16, see, for example, FIG. 4, and 3 wherein Okada discloses the third semiconductor chip 21F is stacked on the second semiconductor chip 21E and offset to expose the plurality of second data pads.
Regarding claim 17, see, for example, FIG. 4, and 3 wherein Okada discloses the fifth semiconductor chip 21G is stacked on the third semiconductor chip 21F and offset to expose the plurality of third data pads.
Regarding claim 18, see, for example, FIG. 4, and 3 wherein Okada discloses the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the fourth semiconductor chip, the fifth semiconductor chip, and the sixth semiconductor chip each further include a plurality of auxiliary pads, and some of the plurality of auxiliary pads of each of the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the fourth semiconductor chip, the fifth semiconductor chip, and the sixth semiconductor chip are command/address pads, which are connected to a controller chip 7, which selects memory chips for programming and reading. Further, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F. 2d 1647 (1987).
Regarding claim 19, Okada does not clearly disclose a buffer chip; however, Keeth
discloses (see, for example, paragraph [0099]) the use of a buffer layer in a memory device. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a buffer layer in order to help drive signals between the dies in the memory stack.
Claim(s) 9, 10, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okada US 2011/0175143 A1 in view of Keeth US 2023/0063029 A1 as applied to claims 3, 5-8, and 11-20, and further in view of Tseng et al. US 2022/0310467 A1. Okada in view of Keeth does not disclose the plurality of first data pads including a plurality of non-functional pads. However, Tseng discloses (see, for example, FIG. 4A, and paragraph [0015]) a semiconductor package 50 comprising an integrated circuit die wherein the integrated circuit die included non-functional pads 56. In paragraph [0011], Tseng discloses the integrated circuit die includes a memory die. It would have been obvious to one of ordinary skill in the art to have a plurality of first data pads including a plurality of non-functional pads, at a time prior to the effective filing date, in order to improve mechanical stability and manufacturing and surface uniformity in the semiconductor package.
Regarding claims 10, and 20, and the limitation “plurality of non-functional pads”, see, for example, the rejection for claim 9 above.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM.
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Eugene Lee
August 11, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815
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