DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I species in the reply filed on 8/14/2026 is acknowledged.
Claim 17-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 8/14/2026.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitations of claim 7 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
It is unclear if applicant is referring to the via and the interconnection or some other region outside the interconnection all the embodiments depict a etch stop outside the interconnection region.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 and 11-12 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claim 7, applicant has not set forth a region outside the interconnect is included as part of the device thus the region lacks antecedent basis. It is unclear if applicant is referring to the via hole or a region not the via hole; if applicant is referring to the via hole applicant should link that region to the recited only portion.
As to claim 11, applicant does not link the structural relationship between the interconnect and the upper etch stop
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, and 5-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wada 8907495.
As to claim 1, Wada teaches A semiconductor device comprising: an insulating structure (at least layer 12,21,22 or 12, 21, 35 see e.g. figures 4 and 6) ; a first interconnection pattern having a first through-hole and disposed on an upper surface of the insulating structure (stack items 22-34); and a conductive via passing through the first through-hole of the first interconnection pattern and contacting the first interconnection pattern on an internal sidewall of the first through-hole (item 40 see e.g. figure 6). Item 33 graphene has different in-plane and out of plane resistivity inherently.
Wada does not specifically teach that the resistance is in the direction of: wherein the first interconnection pattern includes a material having first resistivity in a first direction, parallel to the upper surface of the insulating structure, and second resistivity in a second direction, different from the first direction and not parallel to the upper surface of the insulating structure, and the first resistivity is lower than the second resistivity.
However, the current will flow along the surface parallel to the substrate/insulator since it is a wiring layer. Further there is a known desire to have low resistance wiring along the current flow.
Thus it would have would have been obvious to orient the in plane and out of plane resistance of the graphene so that resistivity in a first direction, parallel to the upper surface of the insulating structure, and second resistivity in a second direction, different from the first direction and not parallel to the upper surface of the insulating structure, and the first resistivity is lower than the second resistivity to reduce the overall resistance along the current flow improving conductivity and reducing heat due to resistance.
b. As to claim 2, Wada teaches wherein the first interconnection pattern and the conductive via comprise different materials
Wada: For the purpose of reducing the contact resistance between the through vias 40 and graphene layers 33, a metal such as Ti, TiN, Ni, Co or the like may be formed on the inner wall surface of the contact hole 41. Further, when the circuit structure is formed to contact the through via 40 only with the graphene wire, it is not always necessary to form a semiconductor element on the lower layer. Alternatively, a structure in which a dummy element region that does not actually function as an element is provided and a through-via 40 is formed therein may be provided. Further, when the circuit structure is formed to directly connect a through via to the semiconductor element 14 without making contact with the graphene layer 33, a structure in which only the through via is directly formed on the semiconductor element without forming a graphene wiring structure in this region may be provided.
c. As to claim 3, Recitation of the word about per the specification paragraph 23:
"About" as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ± 30%, 20%, 10%, 5% of the stated value.
However, this is non-limiting since applicant set forth “For example” about may mean, which is non-limiting since it does not require one to use the limitation as a definition. Thus, the office will apply broadest reasonable interpretation
Wada does not explicitly teach wherein the first interconnection pattern has a width of about 10 nm or less. However, interconnects about 10nm or less were known, about 10 includes 20 nm and 13 nm (using applicant definition of about as 30%).
Line widths of 13 nm for interconnects were known at the time of filing thus it would have been obvious to one of ordinary skill in the art at the time of form the interconnect size to be 13nm since the known trend was to reduce the widths of interconnects (see related, prior art, of applicant paragraph 3 ,thus using conventional size to obtain predictable and desire results for small width lines.
d. As to claim 5, Wada teaches wherein the insulating structure comprises: an intermediate insulating layer (item 12 or 21); and a first etch stop layer disposed between the intermediate insulating layer and the first interconnection pattern (item 21 or 35 or 22 or combinations etch stop is an intended use in a device), wherein the first etch stop layer includes a second through-hole aligned with the first through-hole and through which the conductive via passes (see e.g. figure 6 item 40 passes through layer 22 and 35 and is aligned with the top portion 40).
e. As to claims 6, 13, and 14, Wada depicts a conductive via that has wherein the conductive via has a side surface inclined at a constant angle and wherein the conductive via has a width decreasing in a downward direction.
Further such vias were known in semiconductor processing due to etch limitations.
Thus it would have been obvious to one of ordinary skill in the art at the time of filing to form the via as suggested wherein the conductive via has a side surface inclined at a constant angle and wherein the conductive via has a width decreasing in a downward direction to use convention etch techniques to provide expected outcomes of the via structure as suggested by Wada.
In such an instance Wada further teaches wherein the first etch stop layer comprises a first region located below the first interconnection pattern and a second region excluding the first region (a region directly below the interconnect but not including the edge of the interconnect the second region is below the edge at the via). And, wherein a level of an upper surface of the first region is higher than a level of an upper surface of the second region (due to the slope the second region has an upper surface lower than the portion under the interconnect). Applicant can overcome this rejection by reciting wherein the first etch stop layer comprises a first region located below the first interconnection pattern and a second region excluding the first region and a region below the interconnect, wherein a level of an upper surface of the first region is higher than a level of an upper surface of the second region. Applicant does not define the region to be all of the interconnect thus under BRI Wada modified reads on the claim.
f. As to claim 7, Wherein the device comprises only the via and interconnection there is no etch stop in the via area thus it meet the claim limitation of wherein the first etch stop layer is disposed only below the first interconnection pattern.
g. As to claim 8, Applicant does not distinguish the barrier from the via material. Thus, the fill can be considered a barrier layer and a fill layer thus Wada meets the claim limitation of wherein the conductive via comprises a conductive barrier layer and a via material layer, with the conductive barrier layer formed on a side surface of the via material layer.
h. As to claim 9, Wada under the interpretation of claim 8 teaches wherein the conductive barrier layer is disposed between the internal sidewall of the first through-hole and the via material layer, to directly contact the first interconnection pattern and the via material layer.
i. As to claim 10, Wada teaches wherein the conductive via has an upper surface on a level higher than that of an upper surface of the first interconnection pattern (40 extends higher than the top of 22), and wherein the semiconductor device further comprises an upper etch stop layer disposed on the upper surface of the first interconnection pattern (item 22 or 52 etch stop is an intended use) and including a third through-hole through which the conductive via passes (see item 22 has a via hole through which 40 passes).
j. As to claim 11, Wada teaches at least one of an upper interconnection structure disposed on the first interconnection pattern (item 53) or a lower interconnection structure disposed below the first interconnection pattern, when the conductive via extends in an upward direction to be connected to the upper interconnection structure, a lower surface of the conductive via is coplanar with a lower surface of the first etch stop layer (it is coplanar with layer 21), and (non-elected) when the conductive via extends in a downward direction to be connected to the lower interconnection structure, an upper surface of the conductive via is coplanar with an upper surface of the upper etch stop layer (non-elected).
k. As to claim 12, Wada does not explicitly teach wherein the upper interconnection structure or the lower interconnection structure comprises a second interconnection pattern including a material, identical to that of the first interconnection pattern, wherein the second interconnection pattern includes a fourth through-hole aligned with the first through-hole, and wherein the conductive via simultaneously passes through the first through-hole and the fourth through-hole, and connects the first interconnection pattern and the second interconnection pattern.
However, multilevel wiring were known in the art at the time of filing, and this would further represent a duplication of parts.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to form an upper interconnection pattern including a graphene structure of Wada with a through hole there through in order to provide multi-level low resistance wiring using conventional techniques to obtain the desired low resistance multilayer wiring layers.
l. As to claim 15, Wada teaches Ti, TiN, Ni, Co which are isotropic resistive materials and are not graphene. Cobalt is emphasized since it is the same as applicant paragraph 60.
m. As to claim 16, Wada teaches wherein the first interconnection pattern comprises: an interconnection material layer in which the first resistivity in the first direction is lower than the second resistivity in the second direction (layer 33); and a seed layer disposed below the interconnection material layer and including a material, different from that of the interconnection material layer (layer 32).
Wada states: A second substrate 30 having a graphene layer is formed on the connection insulating film 22. Specifically, a catalyst underlying layer 31 for forming a graphene layer and a catalyst layer 32 are formed on the connection insulating film 22. The catalyst underlying layer 31 is a layer that accelerates the growth of a graphene layer and has a function of crystallinity control of the upper catalyst layer 32 and a function as a catalytic promoter for the growth of a graphene layer. As a typical catalyst underlying layer material, Ti, Ta, Ru, W and the nitride thereof are provided. Further, the oxide of the above metal may be used. Additionally, a stack film obtained by stacking the above films may be used. The catalyst layer 32 is a layer required for forming a graphene layer and is formed continuously to the sidewalls of the wiring structure. As a catalyst material, it is preferable to use a single metal of Co, Ni, Fe, Ru, Cu or the like, an alloy including at least one of them or a carbide of the above material. It is preferable that the catalyst layer 32 is formed of a continuous film and the catalyst layer is required to have a film thickness of at least 0.5 nm or more to form a continuous film.
Co, Ni, Fe, Ru, Cu are all not carbon thus it reads on the claim.
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Chen 20240113024 teaches using multilayer topological interconnects as wiring layers (abstract)
Yoo 20220068824 teaches using a boride the interconnect.
However Wada nor Chen nor Yoo teach and or suggest wherein the first interconnection pattern comprises a conductive material including at least one of an intermetallic compound, an oxide, a carbide, a nitride, or a boride, wherein the intermetallic compound includes a topological semimetal material, the oxide includes a delafossite-based material, and the carbide or the nitride includes a material having an MAX phase in conjunction with the other limitations of claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW L REAMES whose telephone number is (571)272-2408. The examiner can normally be reached M-Th 6:00 am-4:00 pm EST.
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/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/Primary Examiner, Art Unit 2896
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