DETAILED ACTION
This non-final action is responsive to the following communications: application filed on 05/10/2024.
Claims 1-20 are pending. Claims 1, 11, and 20 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. D) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
4. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
No Information Disclosure Statement
5. No IDS has been filed as of this office action date.
Applicant is requested to check all claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 102
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claims 1, 11, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by LEE et al. (US 2025/0227926 A1).
Regarding independent claim 1, LEE teaches a memory device (Fig. 10: 500A “memory device”. See also Fig. 5-Fig. 9 disclosure), comprising:
a memory array structure (Fig. 10: CAS) comprising a plurality of memory banks (Fig. 10: 501, 502 are merged banks),
each of the memory banks (e.g., Fig. 10: 501) comprising a plurality of memory groups (para [0142]: odd word line group and even word line group),
each memory group having at least one memory block (Fig. 10: BLHG1, BLHG2 blocks are contained by odd word line group and even word line group); and
a peripheral structure (Fig. 10: PCS) stacked with the memory array structure (Fig. 10: CAS) in a vertical direction (see Fig. 10 arrangement), and comprising
a plurality of memory-group-driver circuits (Fig. 10: 321 1st SWD, 322 2nd SWD) each corresponding to one of the plurality of memory groups (Fig. 10 in context of para [0136]: “…odd word lines… may be connected to the first SWD 321 and …even word lines, may be connected to the second SWD 322), respectively,
wherein each memory-group-driver circuit (e.g. Fig. 10: 321 1st SWD) is coupled with word lines of the at least one memory block (Fig. 10: odd word lines of BLHG1 and BLHG2) of a corresponding one of the plurality of memory groups (Fig. 10: odd word line group of BLHG1 and BLHG2), and
overlaps with one of the at least one memory blocks in the vertical direction (e.g. Fig. 10: 321 1st SWD overlaps with BLHG1).
Regarding independent claim 11, LEE teaches a method of forming a memory device (although drafted as a method of “forming” memory device, claim 11 does not recite substantive steps and is indistinct from apparatus claim 1, other than the mere presentation of form as a method of forming instead of a device. See Fig. 10: 500A “memory device”. See also Fig. 5-Fig. 9 disclosure), comprising:
forming a memory array structure (Fig. 10: CAS) comprising a plurality of memory banks (Fig. 10: 501, 502),
each of the memory banks (e.g., Fig. 10: 501) comprising a plurality of memory groups (para [0142]: odd word line group and even word line group),
each memory group having at least one memory block (Fig. 10: BLHG1, BLHG2 blocks are contained by odd word line group and even word line group);
forming a peripheral structure (Fig. 10: PCS), comprising
forming a plurality of memory-group-driver circuits (Fig. 10: 321 1st SWD, 322 2nd SWD) each corresponding to one of the plurality of memory groups (Fig. 10 in context of para [0136]: “…odd word lines… may be connected to the first SWD 321 and …even word lines, may be connected to the second SWD 322), respectively; and
bonding the memory array structure and the peripheral structure (para [0045] in context of Fig. 10), such that each memory-group-driver circuit (e.g. Fig. 10: 321 1st SWD) is coupled with word lines of the at least one memory block of a corresponding one of the plurality of memory groups (Fig. 10: odd word line group of BLHG1 and BLHG2), and
overlaps with one of the at least one memory block in a vertical direction (e.g. Fig. 10: 321 1st SWD overlaps with BLHG1).
Regarding independent claim 20, LEE teaches a memory system, comprising: a memory device (Fig. 10: 500A “memory device” and associated system. See also Fig. 5-Fig. 9 disclosure), comprising:
a memory array structure (Fig. 10: CAS) comprising a plurality of memory banks (Fig. 10: 501, 502 are merged banks),
each of the memory banks (e.g., Fig. 10: 501) comprising a plurality of memory groups (para [0142]: odd word line group and even word line group),
each memory group having at least one memory block (Fig. 10: BLHG1, BLHG2 blocks are contained by odd word line group and even word line group), and
a peripheral structure (Fig. 10: PCS) stacked with the memory array structure (Fig. 10: CAS) in a vertical direction (see Fig. 10 arrangement), and comprising
a plurality of memory-group-driver circuits (Fig. 10: 321 1st SWD, 322 2nd SWD) each corresponding to one of the plurality of memory groups (Fig. 10 in context of para [0136]: “…odd word lines… may be connected to the first SWD 321 and …even word lines, may be connected to the second SWD 322), respectively,
wherein each memory-group-driver circuit (See e.g. Fig. 10: 321 1st SWD) is coupled with word lines of the at least one memory block (Fig. 10: odd word lines of BLHG1 and BLHG2) of a corresponding one of the plurality of memory groups (Fig. 10: odd word line group of BLHG1 and BLHG2), and
overlaps with one of the at least one memory blocks in the vertical direction (e.g. Fig. 10: 321 1st SWD overlaps with BLHG1); and
a memory controller coupled with the memory device and configured to control the memory device (para [0040]: “memory controller” function. See also Fig. 11: 2810).
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
10. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
11. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
12. Claims 2-4, and 12-14 is/are rejected under 35 U.S.C. 103 as being obvious over LEE et al. (US 2025/0227926 A1), in view of Jung et al. (US 2025/0166693 A1).
Regarding claim 2, LEE teaches the memory device of claim 1. LEE is silent with respect to the details of memory-group-driver comprising precharge-voltage-driver circuit and discharge-voltage-driver circuit.
Jung teaches each memory-group-driver (Fig. 7: 25 deployed for memory groups) circuit comprises:
a precharge-voltage-driver circuit (Fig. 10: 1001, 1002. See also Fig. 7-Fig. 11) configured to provide a precharge voltage (Fig. 9A, Fig. 10: PXID and associated voltage) to the word lines of the at least one memory block of the corresponding one of the plurality of memory groups (See Fig. 11 blk groups, para [0058]); and
a discharge-voltage-driver circuit (Fig. 10: 1003, 1004, 1006. See also Fig. 7-Fig. 11) configured to provide a discharge voltage (Fig. 10: VBB) to the word lines (Fig. 10: WL) of the at least one memory block of the corresponding one of the plurality of memory groups (See Fig. 11 blk groups; para [0058]).
LEE and Jung are in the same field of endeavor of vertically stacked 3D dram memory integration and they are in analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Jung’s teachings into the apparatus of LEE such that precharge-voltage-driver circuit and discharge-voltage-driver circuit can be implemented to precisely controlling word line charge and thus improve read write operational speed.
Regarding claim 3, LEE and Jung teach the memory device of claim 2.
Jung teaches one of the memory-group-driver circuits (Fig. 7: 25) comprises a buffer circuit configured to buffer control signals of the precharge-voltage-driver circuit or the discharge-voltage-driver circuit (Jung Fig. 9B: 926, 927 combined creates buffer for PXIB signal which controls Fig. 10: 1006); and
the peripheral structure further comprises at least one X-decoder circuit coupled with the buffer circuit, wherein a first X-decoder circuit of the at least one X-decoder circuit is located on the peripheral structure (Fig. 11 in context of para [0058]: row decoder may include MWD, SWD), and
vertically offset from a region of the memory array structure that is between two laterally adjacent memory banks (see Fig. 11: SWD, MWD location in comparison with BLK1, BLK2 intersecting region).
Regarding claim 4, LEE and Jung teach the memory device of claim 3.
LEE teaches wherein the peripheral structure further comprises: a plurality of memory-group-driver-interconnect lines coupled with a corresponding memory-group-driver circuit (see Fig. 9, Fig. 10) and one parity of word lines (para [0136]: SWD connected to one parity of word lines i.e., only even word lines or only odd word lines).
Regarding claim 12, The method of claim 11, wherein forming each memory-group-driver circuit comprises: forming a precharge-voltage-driver circuit configured to provide a precharge voltage to the word lines of the at least one memory block of the corresponding one of the plurality of memory groups; and forming a discharge-voltage-driver circuit configured to provide a discharge voltage to the word lines of the at least one memory block of the corresponding one of the plurality of memory groups. (This claim is drafted as in method format, substantially identical to the limitations recited in claim 2, and is therefore rejected for the same reasons as claim 2)
Regarding claim 13, The method of claim 12, wherein: forming one of the memory-group-driver circuits comprises forming a buffer circuit configured to buffer control signals of the precharge-voltage-driver circuit or the discharge-voltage-driver circuit; and forming the peripheral structure further comprises forming at least one X-decoder circuit coupled with the buffer circuit, wherein after bonding the memory array structure and the peripheral structure, a first X-decoder circuit of the at least one X-decoder circuit is located on the peripheral structure, and vertically offset from a region of the memory array structure that is between two laterally adjacent memory banks. (This claim is drafted as in method format, substantially identical to the limitations recited in claim 3, and is therefore rejected for the same reasons as claim 3)
Regarding claim 14, The method of claim 12, wherein forming the peripheral structure further comprises: forming a plurality of memory-group-driver-interconnect lines configured to couple with a corresponding memory-group-driver circuit and one parity of word lines. (This claim is drafted as in method format, substantially identical to the limitations recited in claim 4, and is therefore rejected for the same reasons as claim 4)
Allowable Subject Matter
Claims 5-10, 15-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 5-10, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the memory device of claim 4, wherein: a subset of the plurality of memory groups are arranged in a row along a first lateral direction; and the memory-group-driver-interconnect lines coupled with the memory-group-driver circuits of the subset of the plurality of memory groups are arranged in a same subset of horizontal routing channels along the first lateral direction.
Regarding claims 15-19, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the method of claim 14, wherein: forming the memory array structure comprises arranging a subset of the plurality of memory groups in a row along a first lateral direction; and forming the peripheral structure further comprises arranging the memory-group-driver-interconnect lines coupled with the memory-group-driver circuits of the subset of the plurality of memory groups in a same subset of horizontal routing channels along the first lateral direction, wherein a number of the horizontal routing channels in the same subset of horizontal routing channels depends on a number of the word lines of each memory block, and is independent of a number of the memory groups in the subset of the plurality of memory groups.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure: Yang (US 2024/0170042 A1): Fig. 1-Fig. 10 disclosure applicable for all claims. US 5448516 A: all figures and disclosure applicable for all claims. KIM et al. (US 2025/0174265 A1) is applicable for all claims. KIM teaches a memory device (“memory device”, see e.g. Fig. 21: 400) comprising: a plurality of sub-array areas each including a plurality of memory cells (Fig. 21: upper, lower portions of MAT1, MAT2); a plurality of contact areas located between the plurality of sub-array areas (para [0190]: “contact”, see e.g., Fig. 21: S1, S2, S3, S4 located between MATs); a plurality of word lines (see e.g. Fig. 21: left MWL1, right MWL1, left MWL2, right MWL2) each extending in a first direction (Fig. 21: horizontal x-direction. See Fig. 6) to cross the plurality of sub- array areas (Fig. 21: upper, lower portions of MAT1, MAT2) and the plurality of contact areas (Fig. 21: SWDL, SWDR area); and a plurality of sub-word line drivers (Fig. 21: G11_SWD, G12_SWD, G21_SWD, G22_SWD) beneath the plurality of sub-array areas (para [0185]: “…sub word line driver circuit…may be positioned underneath the one-side end of the… memory cell mat…”. See also, Fig. 22, Fig. 26A, Fig. 28 disclosure for SWD, MCA arrangement) and configured to drive the plurality of word lines (Fig. 21: MWLs), wherein each of the plurality of contact areas (Fig. 21: SWDL, SWDR area) comprises a plurality of contacts (Fig. 21: S1, S2, S3, S4) electrically connecting a corresponding word line, among the plurality of word lines, to a sub-word line driver (Fig. 21: left MWL1 is connected to G11_SWD via S1, right MWL1 is connected to G21_SWD via S3, left MWL2 is connected to G12_SWD via S2, right MWL2 is connected to G22_SWD via S4).
It is suggested that applicant consider all prior arts made of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825