DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I claims 1-10 and 20 in the reply filed on 08-25-2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claim 10 objected to because of the following informalities:
Applicant stated, “The semiconductor device of claim 9, wherein … and the implanted ions are phosphorus ions or boron ions.” Due to the ‘Or’ limitation in Claim 9 where it states, “a randomly undulating surface or includes implanted ions” Examiner is interpreting the limitations of Claim 10 are also going to be treated as an “or” limitation. Therefore, the ions have already been considered if a reference teaches a randomly undulating surface in Claim 9).
Examiner is requesting the change from And to Or in Claim 10 for the sack of clarity.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "wherein each capacitor further comprises" in line 1. There is insufficient antecedent basis for this limitation in the claim. Examiner believes applicant meant “each vertical capacitor of the array of vertical capacitors” since claim 1 only mentions “an array of vertical capacitors”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jumgmin Park (US 20240363678 A1) hereinafter referred to as “Park”, and further in view of Weng-Yi Chen (US 6207498 B1) hereinafter referred to as “Chen”.
Regarding Claim 1 Park teaches
A semiconductor device, comprising:
an array of vertical transistors (Fig 12 Para [0069]); and
an array of vertical capacitors (Fig 4 Para [0038]) each comprising:
a first electrode structure (BE) coupled with (Fig 12) a corresponding one of the array of vertical transistors, and
a second electrode structure (TE) electrically isolated (220) from the first electrode structure (BE),
wherein the first electrode structure has a first sidewall along a vertical direction and facing the second electrode structure (Fig 4).
Park does not teach
a first uneven sidewall
Chen teaches a similar electrode structure
wherein the first electrode structure (326 Fig 3f) has a first uneven sidewall
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Park such that the first sidewall is a first uneven sidewall, as described in Chen because the modification allows for the electrode to have a relatively large surface area, thus allowing the resultant capacitor to have an increased capacitance (Col 5 lines 55-63)
Regarding Claim 2 Park in view of Chen teaches
The semiconductor device of claim 1,
Park further teaches
wherein each capacitor further comprises:
a capacitor dielectric layer (220) having a thickness between the first electrode structure (BE) and the second electrode structure (TE).
Park further teaches that the thickness of the dielectric layer is a result effective variable that effects the capacitance of the capacitor in tandem with the surface area of the electrode which also effects the capacitance (Para[0004]). Therefore, Park in view of Chen is relied upon to teach
an uneven thickness
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to have the device of Park in view of Chen such that the dielectric layer has an uneven thickness, because the modification of the uneven sidewalls of the electrode, which increases the surface area, and the teaching that the thickness of the dielectric layer as a result effective variable would motive one of ordinary skill in the art to routinely optimize the thickness of the dielectric layer in order to control capacitance. (Park Para [0004])
Regarding Claim 3 Park in view of Chen teaches
The semiconductor device of claim 1, wherein:
Park further teaches
the second electrode structures (TE) of the array of vertical capacitors are connected with each other (Fig 4 Para [0042]) to form a common electrode.
Regarding Claim 4 Park in view of Chen teaches
The semiconductor device of claim 1, wherein:
Park further teaches
the second electrode structure (TE) has a second sidewall facing the first electrode structure (BE) (Fig 4).
Park does not teach
a second uneven sidewall
Chen teaches increasing the surface area of an electrode structure and therefore is relied upon to teach
the second electrode structure has a second uneven sidewall
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Park in view of Chen such that the second sidewall is a second uneven sidewall, as described in Chen because the modification allows for the electrode to have a relatively large surface area, thus allowing the resultant capacitor to have an increased capacitance (Col 5 lines 55-63)
Regarding Claim 7 Park in view of Chen teaches
The semiconductor device of claim 1,
wherein the first uneven sidewall has a waved surface. (Chen Fig 3f shows at least on portions a repeating pattern therefore a waved surface)
Regarding Claim 8 Park in view of Chen teaches
The semiconductor device of claim 7, wherein:
Park in view of Chen does not explicitly teach
a lateral difference between a peak position and a trough position of the waved surface of the first uneven sidewall is in a range between about 10 nm and about 15 nm; and
a vertical difference between adjacent two peak positions of the waved surface of the first uneven sidewall is in a range between about 10 nm and about 30 nm.
Chen, however, does teach that the waved sidewalls directly determine the electrodes surface area and that the surface area of the electrodes is a result effective variable that determines the capacitance of the capacitor. Therefore, It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the size and shape of the waved sidewall such that the surface area is routinely optimized to give the desired capacitance, as described in Chen. (Chen Col 5 lines 55-63)
Regarding Claim 9 Park in view of Chen teaches
The semiconductor device of claim 1, wherein:
the first uneven sidewall has a randomly undulating surface (Chen fig 3f) or includes implanted ions with a randomly distributed concentration.
Regarding Claim 10 Park in view of Chen teaches
The semiconductor device of claim 9, wherein:
Park in view of Chen does not explicitly teach
a lateral difference between a peak position and a trough position of the randomly undulating surface of the first uneven sidewall is in a range between about 2 nm and about 8 nm; and the implanted ions are phosphorus ions or boron ions. (the ions have already been considered because Chen teaches a randomly undulating surface in Claim 9)
Chen, however, does teach that the waved sidewalls directly determine the electrodes surface area and that the surface area of the electrodes is a result effective variable that determines the capacitance of the capacitor. Therefore, It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the size and shape of the waved sidewall such that the surface area is routinely optimized to give the desired capacitance, as described in Chen. (Chen Col 5 lines 55-63)
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Chen as applied to claim 1 above, and further in view of Sang-Yun Lee (US 20220139920 A1) hereinafter referred to as “Lee”.
Regarding Claim 5 Park in view of Chen teaches
The semiconductor device of claim 1, further comprising:
Park further teaches
a structure (232 and/or 230) in between adjacent vertical capacitors of the array of vertical capacitors, wherein the first electrode structure (BE) has a smooth sidewall facing the structure.
Park in view of Chen does not teach this structure being
a mesh structure
Lee teaches a similar structure that is
a mesh structure (239 Para [0062])
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Park in view of Chen such that the structure is a mesh structure, as described in Lee because the modification allows for the mesh layer to act as a support that helps to prevent toppling. (Lee Para [0062])
Regarding Claim 6 Park in view of Chen teaches
The semiconductor device of claim 1, further comprising:
Park further teaches
a structure (232 and/or 230) in between adjacent vertical capacitors of the array of vertical capacitors, wherein a portion of the first electrode structure (BE) in contact with the structure has a smooth sidewall. (Fig 4)
Park in view of Chen does not teach this structure being
a mesh structure
Lee teaches a similar structure that is
a mesh structure (239 Para [0062])
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Park in view of Chen such that the structure is a mesh structure, as described in Lee because the modification allows for the mesh layer to act as a support that helps to prevent toppling. (Lee Para [0062])
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Chen and further in view of Lee
Regarding Claim 20 Park teaches
A system, comprising:
a memory device (Fig 4) configured to store data (Para [0003]-[0004]), the memory device comprising:
an array of vertical transistors (Fig 12 Para [0069]); and
an array of vertical capacitors (Fig 4 Para [0038]) each comprising:
a first electrode structure (BE) coupled with (Fig 12) a corresponding one of the array of vertical transistors, and
a second electrode structure (TE) electrically isolated (220) from the first electrode structure, wherein
the first electrode structure (BE) has a first sidewall along a vertical direction and facing the second electrode structure; and
Park does not explicitly teach
a first uneven sidewall
a memory controller electrically connected to the memory device and configured to control the memory device.
Chen teaches a similar electrode structure and memory structure
a first uneven sidewall (326 Fig 3f)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Park such that the first sidewall is a first uneven sidewall, as described in Chen because the modification allows for the electrode to have a relatively large surface area, thus allowing the resultant capacitor to have an increased capacitance (Col 5 lines 55-63).
Park in view of Chen do not explicitly teach
a memory controller
Lee teaches a Memory device
a memory controller (Para [0003]) electrically connected to the memory device and configured to control the memory device.
And it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Park in view of Chen such that the memory device has a memory device controller, as described in Lee because the modification allows for the issuance of refresh commands. (Lee Para [0003])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Park; Chanro (US-12356638-B2), Frost; Denzil S. (US-20250372505-A1), Schultz; Richard T. (US-20180277624-A1)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAIME LYNN SPRENGER whose telephone number is (571)272-8444. The examiner can normally be reached Monday - Friday, 9:00a.m. - 5:00p.m. ET..
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/JAIME LYNN SPRENGER/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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