Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/660,895 filed on 05/10/2024.
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-17), drawn to the device invention, and within Group I, election of Species I (claims 1-10) in the reply filed on 06/08/2026 is acknowledged.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pub # 2005/0006704 to Ning et al. (Ning).
Regarding independent claim 1, Ning discloses a semiconductor structure (Figs. 3A-3J), comprising:
a lower semiconductor layer (Fig. 3A: 10);
an upper semiconductor layer (Fig. 3A: 14); and
an insulating layer (Fig. 3A: 12) between the lower semiconductor layer (10) and the upper semiconductor layer (14),
wherein a first thickness (T2) of the upper semiconductor layer (14) in a first region (see Examiner’s Mark-up below) is greater than a second thickness (T1) of the upper semiconductor layer (14) in a second region (see Examiner’s Mark-up below).
PNG
media_image1.png
196
793
media_image1.png
Greyscale
Regarding claim 2, Ning discloses wherein: the lower semiconductor layer (10) and the upper semiconductor layer (14) comprise silicon (¶0050-0051); and the insulating layer (12) comprises silicon oxide (¶0015).
Regarding claim 3, Ning discloses wherein: the insulating layer (12) extends in the first region and the second region (see Examiner’s Mark-up above in claim 1); and the lower semiconductor layer (10) is separated from the upper semiconductor layer (14) comprising silicon by the insulating layer (12).
Regarding claim 4, Ning discloses wherein: a first upper surface (see Examiner’s Mark-up below) of the upper semiconductor layer (14) in the first region is higher than a second upper surface (see Examiner’s Mark-up below) of the upper semiconductor layer (14) in the second region.
Regarding claim 7, Ning discloses wherein: a thickness of the insulating layer (12) is in a range between 10nm and 30nm (¶0019). Ning specifically discloses a semiconductor structure including lower semiconductor layer 10, insulating layer 12, and upper semiconductor layer 14 (Fig. 3A). ¶0019 teaches that insulating layer 12 has a thickness of about 1 nm to about 1000 nm, and more preferably about 20 nm to about 200 nm. The claimed thickness range of 10 nm to 30 nm overlaps the expressly disclosed preferred thickness range of 20 nm to about 200 nm and is encompassed within the broader disclosed range. Accordingly, the claimed thickness limitation is anticipated by the Ning.
Regarding claim 10, Ning discloses wherein a first material of the upper semiconductor layer (14) is same as a second material of the lower semiconductor layer (10) (see ¶0019).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2005/0006704 to Ning et al. (Ning) in view of US Pub # 2003/0146488 to Nagano et al. (Nagano).
Regarding claim 5, Ning disclose all of the limitations of claim 1 from which this claim depends. Ning specifically teaches a semiconductor structure including a lower semiconductor layer 10, an upper semiconductor layer 14, and an insulating layer 12 disposed between the lower semiconductor layer 10 and the upper semiconductor layer 14 (Fig. 3A).
Ning, however, does not expressly teach that the insulating layer extends in the second region while without in the first region and the lower semiconductor layer is in contact with the upper semiconductor layer comprising silicon in the first region.
Nagano teaches a partial SOI substrate (Fig. 1A) and completed device fabricated on that substrate (Fig. 8) in which the insulating layer (Fig. 1A: 2) is extends only in the SOI region (SOI region correspond to the second region) beneath the upper semiconductor layer (Fig. 1A: 3 and 5, under BRI, the combination of layer 3 and 5 is presently considered to be the upper semiconductor layer as claimed) without in the first region, while the non-SOI region (correspond to the first region), and the lower semiconductor layer (1) is in contact with the upper semiconductor layer (3 and 5) comprising silicon in the first region (¶0037).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to modify the semiconductor structure of Ning to provide the insulating layer only in selected regions as taught by Nagano in order to obtain the well-known advantages of integrating SOI and bulk semiconductor regions on the same substrate, thereby permitting different device types to be fabricated on a common wafer while optimizing electrical performance and manufacturing flexibility (see paragraphs corresponding to Fig. 1A and Fig. 8).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2005/0006704 to Ning et al. (Ning) in view of US Pub # 2003/0146488 to Nagano et al. (Nagano) and further in view of US Pub # 2004/0219761 to Fuselier et al. (Fuselier).
Regarding claim 6, Ning as previously modified disclose teach all of the limitations of claim 5 from which this claim depends. Ning as previously modified specifically teaches a semiconductor structure including a lower semiconductor layer, an upper semiconductor layer, and an insulating layer disposed only in one lateral region between the lower and upper semiconductor layers (see the rejections of claims 1 and 5 above).
Ning as previously modified, however, does not expressly teach wherein a thickness of the insulating layer is in a range between 10nm and 30nm.
Fuselier further teaches forming a substantially planar or flush upper semiconductor surface by performing a chemical mechanical polishing (CMP) process. Specifically, Figure 3E shows semiconductor layer 58 prior to polishing, Figure 3F shows removal of upper portion 59 by CMP, resulting in active semiconductor layer 21 over buried oxide portions 20A and 20B, as described in (¶0029).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to perform the CMP process taught by Fuselier on the semiconductor structure of the Ning as previously modified in order to planarize the upper semiconductor surface, thereby providing the claimed flush upper surface and facilitating subsequent semiconductor fabrication processes (¶0029).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2005/0006704 to Ning et al. (Ning) in view of US Pub # 2004/0121547 to Lee et al. (Lee).
Regarding claim 8, Ning disclose all of the limitations of claim 1 from which this claim depends. Ning specifically teaches a semiconductor structure including a lower semiconductor layer 10, an insulating layer 12, and an upper semiconductor layer 14 (Fig. 3A). Ning further teaches that various semiconductor devices, including CMOS transistors and vertical bipolar transistors, may be integrated on the same SOI chip (¶0007, 0047– 0049). Ning therefore teaches forming transistor devices in the upper semiconductor layer of an SOI substrate.
However, Ning does not expressly teach a first group of transistors having a first operating voltage formed in the upper semiconductor layer in a first region, and a second group of transistors having a second operating voltage lower than the first operating voltage formed in the upper semiconductor layer in a second region.
Lee teaches an SOI semiconductor structure having separate high-voltage device regions and low-voltage device regions formed on the same SOI substrate (e.g., Figure 3 and the corresponding description). Lee teaches that the SOI substrate includes a lower semiconductor substrate (300), a buried insulating layer (302), and an upper semiconductor layer (314), with high-voltage transistors formed in one region and low-voltage transistors formed in another region to accommodate different operating voltages (¶0033-0034).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to modify the SOI semiconductor structure of Ning to incorporate separate high-voltage and low-voltage transistor regions as taught by Lee in order to integrate devices requiring different operating voltages on a common SOI substrate while maintaining the performance and isolation advantages of SOI technology (¶0033-0034 and 0041). Such a modification merely applies a known SOI device arrangement to the SOI substrate of Ning for its recognized benefits.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2005/0006704 to Ning et al. (Ning) in view of US Pub # 2008/0050887 to Chen et al. (Chen).
Regarding claim 9, Ning disclose all of the limitations of claim 1 from which this claim depends. Ning specifically teaches a semiconductor structure including lower semiconductor layer 10, insulating layer 12, and upper semiconductor layer 14 (Fig. 3A).
However, Ning does not expressly teach wherein a first material of the upper semiconductor layer is different from a second material of the lower semiconductor layer.
Chen teaches a semiconductor-on-insulator structure including substrate 12, buried insulator layer 14, and a Ge-containing semiconductor layer 18 disposed above the buried insulator (Fig. 1). The specification explains that substrate 12 is preferably a Si-containing substrate, whereas semiconductor layer 18 is Ge-containing, thereby teaching different semiconductor materials for the upper and lower semiconductor layers.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to substitute the upper silicon-containing semiconductor layer of Ning with the Ge-containing semiconductor layer taught by Chen in order to obtain the recognized material-dependent electrical advantages of germanium-containing device layers, such as enhanced carrier mobility and improved device performance, while maintaining the conventional SOI substrate structure (¶0005 and 0007).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pat # 7,833,849 to Callegari et al., US Pat # 7,122,864 to Nagano et al., US Pub # 2006/0063356 to Park et al., US Pat # 6,737,332 to Fuselier et al. and US Pat # 6448114 to An et al.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHSEN AHMADI whose telephone number is (571)272-5062. The examiner can normally be reached M-F: 9:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William F Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHSEN AHMADI/Primary Examiner, Art Unit 2896
Prosecution Insights