DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “thickness view” in claim 1,2, and 4 is used by the claim to mean “the plan view,” while the accepted meaning is “in the z direction.” The term is indefinite because the specification does not clearly redefine the term. In this instant case, the corner portion is not shown in the thickness view but it is shown in the plan view by figures 8,9, and 10.
For the purpose of compact prosecution, the Examiner has interpreted claims 1, 2 and 4 to mean the plan view or top-down view. Furthermore, the z-axis view for the remaining dependent claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 17 is rejected under pre-AIA 35 U.S.C. 102(a)(1) as being anticipated by Tanaka (WO 2020012958 A1, machine translation included).
Regarding claim 17, Tanaka teaches a semiconductor device (¶0066, fig 26: B10) comprising:
a semiconductor element (¶0066, fig 26: A10) according to claim 1;
a die pad portion (¶0067, fig 26: 51) on which the semiconductor element is mounted (Tanaka fig 26: A10 is mounted on 51);
a sealing resin (¶0066, fig 26: 70) covering at least a part of the die pad portion (fig 26: 51) and the semiconductor element (fig 26: A10); and
a terminal portion (¶0066, fig 26: 52) protruding from the sealing resin (fig 26:70) and electrically connected to the semiconductor element (¶0077, fig 26: 52 protruding from 70 and electrically connected to A10).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-16 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka in view of Dubey et. al. (US 20160233175 A1).
Regarding claim 1, Tanaka teaches a semiconductor element (¶0045, fig 3: A10) comprising:
an element body (¶0016, fig 3:10) including an obverse surface facing one side in a thickness direction;
a wiring layer (¶0016, fig 3: 14) formed on the obverse surface (¶0015, fig 3: 10A main surface) and electrically connected to the element body (¶0021, fig 3: 14 on 10a is electrically connected to 10) ; and
an obverse-surface electrode (¶0021, fig 3: composite electrode 21/23) formed on and electrically connected to the wiring layer (fig 3: 14) (¶0021, fig 3: 32 formed on and electrically connected to 14),
wherein an outer edge of the obverse-surface electrode (fig 3: 21, main electrode) includes a corner portion (annotated fig 3: corner where electrode sides touch) as viewed in the thickness direction (¶0019, fig 3: top-down view),
PNG
media_image1.png
387
553
media_image1.png
Greyscale
the wiring layer (fig 3: 14) includes a first edge extending along the outer edge of the obverse-surface electrode (fig 3: 21) as viewed in the thickness direction (¶0019,14 is located under 21 and 23, and extends along the outer edge of 21).
13) , and a second edge (annotated fig 1: second edge) connected to the first edge (annotated fig. 1: first edge) and facing the corner portion as viewed in the thickness direction (¶0019, fig 1: 14 is underneath 21, facing corner portion with the same dimensions as shown in fig 3).
PNG
media_image2.png
391
553
media_image2.png
Greyscale
Tanaka does not explicitly teach the second edge includes a portion that defines, as viewed in the thickness direction, a distance from the second edge to the outer edge of the obverse-surface electrode in a direction perpendicular to the second edge, the distance being greater than a distance from the first edge to the outer edge of the obverse-surface electrode in a direction perpendicular to the first edge.
Dubey teaches a semiconductor element (fig 12: 110 semiconductor die) with a second edge (fig 12: second edge) to the outer edge being the greater from a first edge (annotated fig 12: edges of 116.sub.1 ) to the outer edge (annotated fig 12: edges of 142).
PNG
media_image3.png
304
438
media_image3.png
Greyscale
.
It would have been obvious to one of the ordinary skill in the art at the time the invention was filed to configure the second edges of the wiring layer to the electrode second edge to be larger than the distance from the first edge of the wiring layer to the first side of the electrode to optimize the amount of space for the wiring layer and decrease stress on the corner portions (Dubey ¶0029). In this instant case, the wiring layer is further away from the second edge to prevent the corner concentration points from cracking. The distance from wiring edge to the first edge is a matter of routine optimization as means to increase capacity in the semiconductor device.
Regarding claim 2, Tanaka in view of Dubey teaches the semiconductor element according to claim 1, wherein the outer edge (Tanaka fig 1: combination of side edges of electrode, and corner portions) of the obverse-surface electrode (Tanaka fig 1: composite electrode 21/23) includes a side end (Tanaka annotated fig 1: side end of electrode) that is connected to the corner portion (Tanaka annotated fig 1: corner portion) and parallel to the first edge (Tanaka annotated figure 1: side edge of electrode is connected to the corner portion and parallel to first edge of wiring layer), and
the corner portion is linear as viewed in the thickness direction (Tanaka fig 1: top-down view) and inclined to the side end as viewed in the thickness direction (Tanaka annotated fig 1: . corner portion is linear and makes an angle with side end of electrode)
PNG
media_image4.png
413
555
media_image4.png
Greyscale
Regarding claim 3, Tanaka in view of Dubey teaches the semiconductor element according to claim 2, including an obverse-surface electrode (fig 1 and 7: 10a)
Tanaka in view of Dubey as modified above does not teach an obverse surface electrode has an octagonal shape as viewed in the thickness direction.
However, Dubey teaches an octagonal shape as view in the thickness direction.
It would have been obvious to one of ordinary skill in the art at the time the
invention was filed to configure the electrode in figure 1 with eight sides like the
element in Dubey to reducing stresses by distributing stress to more points, reducing
delamination and cracking failures (Dubey ¶0030).
Regarding claim 4, Tanaka in view of Dubey teach the semiconductor element according to claim 2, wherein the obverse-surface electrode (Tanaka fig 1and 7: composite electrode 21/23) includes a main portion (Tanaka fig 1: 21) having the corner portion (Tanaka annotated fig 1: corner portion) and the side end (fig 1 and 7: side end of electrode) and overlapping with the wiring layer (Tanaka annotated fig 1: wiring layer) as viewed in the thickness direction (Tanaka fig 1: top down view) (Tanaka, annotated fig 1: composite 21/23 includes 21 with a corner portion, and side end of the electrode overlapping the wiring layer located underneath view in the top down view).
PNG
media_image4.png
413
555
media_image4.png
Greyscale
Regarding claim 5, Tanaka in view of Dubey teach the semiconductor element according to claim 4, further comprising an insulating film interposed (Tanaka ¶0015, fig 3 and fig 7: 13) between the main portion (Tanaka fig 3: 21) and the wiring layer (fig 7: 14) in the thickness direction (fig 7: z direction).
Regarding claim 6, Tanaka in view of Dubey teach the semiconductor element according to claim 5, wherein the obverse-surface electrode (Tanaka fig 3: composite electrode 21/23) includes a plurality of penetrating portions (Tanaka ¶0021, fig 7: 211) passing through the insulating film (Tanaka ¶0015, fig 7: 13) and electrically connecting the main portion (Tanaka fig 3: 21) and the wiring layer (Tanaka fig 7: 14).
Regarding claim 7, Tanaka in view of Dubey teach the semiconductor element according to claim 6, wherein the wiring layer includes an edge portion (Tanaka annotated fig 1 and fig 7: side end of 21) located between the plurality of penetrating portions (Tanaka ¶0020, annotated fig 7: extended portion of 211), and
PNG
media_image5.png
288
482
media_image5.png
Greyscale
the first edge (Tanaka fig 1/7: first edge of wiring layer) as viewed in the thickness direction (fig 1: top-down view), and
the edge portion (Tanaka annotated fig 1 and fig 7: side end of 21) is formed with at least one slit (Tanaka ¶0046, fig 7: opening 131).
PNG
media_image6.png
288
713
media_image6.png
Greyscale
Regarding claim 8, Tanaka in view of Dubey teach the semiconductor element according to claim 7, wherein the edge portion (annotated fig 1 and fig 7: side end of 21) is formed with a plurality of slits (fig 7: opening 131), and
the plurality of slits are arranged along the first edge (fig 1/7: first edge of 14) (fig 7: side end of 21 is formed with 131, and the plurality of 131 are along the edge of 14).
PNG
media_image7.png
308
632
media_image7.png
Greyscale
Regarding claim 9, Tanka in view of Dubey teaches the semiconductor element according to claim 1, including a wiring layer (Tanaka fig 3: 14).
Tanaka in view of Dubey as applied to claim 1, does not teach wherein the wiring layer includes an L-shaped cutout having the second edge.
However, Dubey teaches a semiconductor die a semiconductor die (¶0033, fig 12: 116.sub.1) that includes an L-shaped cutout (¶0033, fig 12: 182 side elements) having a second edge (annotated fig 12: second edge).
PNG
media_image8.png
304
438
media_image8.png
Greyscale
It would have been obvious to one of ordinary skill in the art at the time the
invention was filed to configure the wiring layer with L- shaped cutouts like the
element in Dubey to reduce stress (Dubey, ¶0033, fig 12).
Regarding claim 10 Tanaka in view of Dubey teach the semiconductor element according to claim 1, wherein the wiring layer (Tanaka fig 7: 14) includes a first layer (Tanaka ¶0047, fig 7: 141) and a second layer (Tanaka ¶0047, fig 7: 143) stacked and spaced apart from each other in the thickness direction (Tanaka fig 7: top down) (fig 7: 141 and 143 are stacked and spaced apart in the top down direction), and a plurality of vias (Tanaka ¶0047 fig 7: 142/144, plurality of first and second vias) electrically connecting the first layer and the second layer (Tanaka ¶0047, fig 7: 144 electrically connected to metal wiring layers 141 and 143) .
PNG
media_image9.png
308
492
media_image9.png
Greyscale
Regarding claim 11, Tanaka in view of Dubey teach the semiconductor element according to claim 10, further comprising an interlayer insulating layer (Tanaka ¶0046, fig 7: 13) located between the first layer (Tanaka ¶0047, fig 7: 141) and the second layer (Tanaka ¶0047, fig 7: 143), and
the plurality of vias (Tanaka ¶0047: 142/144) pass through the interlayer insulating layer in the thickness direction (Tanaka ¶0047, fig 7: 13 is between 141 and 143, and 142/144 pass through 13 in the top-down direction).
Regarding claim 12, Tanaka in view of Dubey teach the semiconductor element according to claim 1, wherein the wiring layer (Tanaka fig 7: 14) contains aluminum, and
the obverse-surface electrode (Tanaka fig 3: 21) contains copper (Tanaka ¶0019, 14 contains Aluminum and Copper).
Regarding claim 13, Tanaka in view of Dubey teach the semiconductor element according to claim 1, wherein the element body (Tanaka ¶0013, fig 1: 10) includes a switching circuit (Tanaka ¶0013, fig 1: 30) and a control circuit (Tanaka ¶0013, fig 1: 40).
Regarding claim 14, Tanaka in view of Dubey teach the semiconductor element according to claim 13, wherein the obverse-surface electrode (Tanaka fig 3: composite electrode 21/23) includes a first portion (Tanaka fig 3: 21) and a second portion (Tanaka fig 3: 23) spaced apart from each other (fig 3:21 and 23 are spaced apart from each other),
the first portion (Tanaka fig 3: 21) overlaps with the switching circuit (Tanaka fig 3: 30) as viewed in the thickness direction, and
the second portion (Tanaka fig 3: 23) overlaps with the control circuit (Tanaka fig 3: 40) as viewed in the thickness direction (Tanaka fig 3: z direction).
Regarding claim 15, Tanaka in view of Dubey teach the semiconductor element according to claim 13, further comprising a reverse-surface electrode (Tanaka fig 3: composite electrode 21/23),
wherein the element body (Tanaka ¶0016, fig 3: 10) includes a reverse surface (Tanaka ¶0016, fig 3: 10B) facing an opposite side from the obverse surface (Tanaka fig 3: 10A) (Tanaka ¶0015, fig 3: 10 includes 10B facing an opposite side from 10A), and
the reverse-surface electrode (Tanaka ¶0029, fig 3: 22 backside electrode) is provided on the reverse surface (Tanaka fig 3: 10B) and electrically connected to the switching circuit.
Regarding claim 16, Tanaka in view of Dubey teach the semiconductor element according to claim 1, wherein the element body (Tanaka fig 3: 10) contains silicon (Tanaka ¶0016, fig 3: substrate of 11 is made out of silicon).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LYTESHIA M PRICE whose telephone number is (571)270-0132. The examiner can normally be reached 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LYTESHIA M PRICE/Examiner, Art Unit 2818
/BRIAN TURNER/Primary Examiner, Art Unit 2818
Prosecution Insights