Prosecution Insights
Last updated: May 29, 2026
Application No. 18/660,925

Multi-Instruction Packing In Single Instruction Slot

Non-Final OA §112
Filed
May 10, 2024
Examiner
VICARY, KEITH E
Art Unit
2183
Tech Center
2100 — Computer Architecture & Software
Assignee
Google LLC
OA Round
3 (Non-Final)
58%
Grant Probability
Moderate
3-4
OA Rounds
1y 10m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 58% of resolved cases
58%
Career Allowance Rate
393 granted / 684 resolved
+2.5% vs TC avg
Strong +41% interview lift
Without
With
+41.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 11m
Avg Prosecution
27 currently pending
Career history
728
Total Applications
across all art units

Statute-Specific Performance

§101
7.2%
-32.8% vs TC avg
§103
48.9%
+8.9% vs TC avg
§102
7.2%
-32.8% vs TC avg
§112
32.3%
-7.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 684 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 5, 2025, has been entered. Claims 1-20 are pending in this office action and presented for examination. Claims 1, 9, 11, and 20 are newly amended by the RCE received December 18, 2025. Drawings The drawings are objected to because: In FIG. 1, “Opcode 1” and “Opcode 2” are newly underlined, leading to a) a lack of clarity regarding whether “1” and “2” are reference characters, and b) if so, a lack of mention in the specification of “1” and “2”. Similarly, see “Opcode 1”, “Opcode 2”, and “Opcode 3” in FIG. 3. Examiner recommends, throughout the figures, removing underlines from all text and numbers that are not reference characters. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 1 recites the limitation “receive an instruction including a slot corresponding to an execution unit” in line 5. Claim 1 further recites the limitation “determine a first operation of the instruction for the slot by extracting a first operation code from the instruction … assign the first operation to the slot by adding the first operation code to the slot; determine a second operation of the instruction for the slot based on the first operation by extracting a second operation code from the instruction … assign the second operation to the slot by adding the second operation code to the slot” in lines 6-14. However, the original disclosure does not appear to provide support for these limitations. For example, in the former limitation, “a slot” appears to be a slot of an instruction of instructions 212. Regarding this particular instruction, see, for example, paragraph [0030] (“The multi-instruction packing system 200 can be configured to receive instructions 212 by fetching the instructions. The instructions 212 can also be provided to the multi-instruction packing system 200 through a storage medium, such as main memory 202”); paragraph [0031] (“From the instructions 212, the multi-instruction packing system 200 can be configured to output one or more results generated as output data 214”); paragraph [0033] (“The decoding engine 204 can be configured to decode the instruction fetched from the main memory 202. The decoding engine 204 can decode instructions into operations and extract opcodes from the instruction. The extracted opcodes can be placed into an ALU slot”); paragraph [0054] (“As shown in block 510, the multi-instruction packing system 200 receives an instruction by fetching the instruction from a storage medium. The instruction can include one or more slots corresponding to respective execution units such as ALUs. The multi-instruction packing system 200 extracts one or more opcodes by decoding the one or more slots”). However, in the latter limitation, “the slot” instead appears to be a slot of an instruction of Output Data 214 of FIG. 2. Regarding this particular instruction, see, for example, paragraph [0031] (“the multi-instruction packing system 200 can be configured to provide the output data 204 to the ALU as a set of computer-readable instructions); paragraph [0035] (“A packing engine 208 can be configured to encode an instruction for the first and second operations … The packing engine 208 then can store the packed instruction to the main memory 202 as output 214”); paragraph [0036] (“ALU can be configured to process the first and second opcodes based on the packing (sic) instruction”); paragraph [0037] (“The output data 214 can follow the instruction format including the first opcode and the second opcode. FIG. 3 depicts a block diagram of an example instruction format 300 for executing the one or more operations. An instruction can include one or more slots such as slots 340 and 350”). Therefore, the original disclosure does not appear to provide support for the former limitation in conjunction with the latter limitation, given that, for example, the original disclosure does not appear to provide support for the slot of the latter limitation and the slot of the former limitation being the same slot (i.e., being located in a same instruction). Claims 2-10 are rejected for failing to alleviate the rejection of claim 1 above. Claim 11 recites the limitation “receive … an instruction including a slot corresponding to an execution unit” in lines 2-3. Claim 11 further recites the limitation “determining … a first operation for the slot by extracting a first operation code from the instruction … assigning … the first operation to the slot by adding the first operation code to the slot; determining … a second operation of the instruction for the slot based on the first operation by extracting a second operation code from the instruction … assigning the second operation to the slot by adding the second operation code to the slot” in lines 4-14. However, the original disclosure does not appear to provide support for these limitations. For example, in the former limitation, “a slot” appears to be a slot of an instruction of instructions 212. Regarding this particular instruction, see, for example, paragraph [0030] (“The multi-instruction packing system 200 can be configured to receive instructions 212 by fetching the instructions. The instructions 212 can also be provided to the multi-instruction packing system 200 through a storage medium, such as main memory 202”); paragraph [0031] (“From the instructions 212, the multi-instruction packing system 200 can be configured to output one or more results generated as output data 214”); paragraph [0033] (“The decoding engine 204 can be configured to decode the instruction fetched from the main memory 202. The decoding engine 204 can decode instructions into operations and extract opcodes from the instruction. The extracted opcodes can be placed into an ALU slot”); paragraph [0054] (“As shown in block 510, the multi-instruction packing system 200 receives an instruction by fetching the instruction from a storage medium. The instruction can include one or more slots corresponding to respective execution units such as ALUs. The multi-instruction packing system 200 extracts one or more opcodes by decoding the one or more slots”). However, in the latter limitation, “the slot” instead appears to be a slot of an instruction of Output Data 214 of FIG. 2. Regarding this particular instruction, see, for example, paragraph [0031] (“the multi-instruction packing system 200 can be configured to provide the output data 204 to the ALU as a set of computer-readable instructions); paragraph [0035] (“A packing engine 208 can be configured to encode an instruction for the first and second operations … The packing engine 208 then can store the packed instruction to the main memory 202 as output 214”); paragraph [0036] (“ALU can be configured to process the first and second opcodes based on the packing (sic) instruction”); paragraph [0037] (“The output data 214 can follow the instruction format including the first opcode and the second opcode. FIG. 3 depicts a block diagram of an example instruction format 300 for executing the one or more operations. An instruction can include one or more slots such as slots 340 and 350”). Therefore, the original disclosure does not appear to provide support for the former limitation in conjunction with the latter limitation, given that, for example, the original disclosure does not appear to provide support for the slot of the latter limitation being the same as the slot of the former limitation. Claims 12-19 are rejected for failing to alleviate the rejection of claim 11 above. Claim 20 recites the limitation “receiving an instruction including a slot corresponding to an execution unit” in line 4. Claim 20 further recites the limitation “determining a first operation of the instruction for the slot by extracting a first operation code from the instruction … assigning the first operation to the slot by adding the first operation code to the slot; determining a second operation of the instruction for the slot based on the first operation by extracting a second operation code from the instruction … assigning the second operation to the slot by adding the second operation code to the slot” in lines 5-13. However, the original disclosure does not appear to provide support for these limitations. For example, in the former limitation, “a slot” appears to be a slot of an instruction of instructions 212. Regarding this particular instruction, see, for example, paragraph [0030] (“The multi-instruction packing system 200 can be configured to receive instructions 212 by fetching the instructions. The instructions 212 can also be provided to the multi-instruction packing system 200 through a storage medium, such as main memory 202”); paragraph [0031] (“From the instructions 212, the multi-instruction packing system 200 can be configured to output one or more results generated as output data 214”); paragraph [0033] (“The decoding engine 204 can be configured to decode the instruction fetched from the main memory 202. The decoding engine 204 can decode instructions into operations and extract opcodes from the instruction. The extracted opcodes can be placed into an ALU slot”); paragraph [0054] (“As shown in block 510, the multi-instruction packing system 200 receives an instruction by fetching the instruction from a storage medium. The instruction can include one or more slots corresponding to respective execution units such as ALUs. The multi-instruction packing system 200 extracts one or more opcodes by decoding the one or more slots”). However, in the latter limitation, “the slot” instead appears to be a slot of an instruction of Output Data 214 of FIG. 2. Regarding this particular instruction, see, for example, paragraph [0031] (“the multi-instruction packing system 200 can be configured to provide the output data 204 to the ALU as a set of computer-readable instructions); paragraph [0035] (“A packing engine 208 can be configured to encode an instruction for the first and second operations … The packing engine 208 then can store the packed instruction to the main memory 202 as output 214”); paragraph [0036] (“ALU can be configured to process the first and second opcodes based on the packing (sic) instruction”); paragraph [0037] (“The output data 214 can follow the instruction format including the first opcode and the second opcode. FIG. 3 depicts a block diagram of an example instruction format 300 for executing the one or more operations. An instruction can include one or more slots such as slots 340 and 350”). Therefore, the original disclosure does not appear to provide support for the former limitation in conjunction with the latter limitation, given that, for example, the original disclosure does not appear to provide support for the slot of the latter limitation being the same as the slot of the former limitation. Response to Arguments Applicant on page 8 argues: "The abstract was objected to due to an informality, which has been addressed in the above amendments to the abstract. Therefore, Applicant respectfully requests withdrawal of the specification objections.” In view of the aforementioned amendment, the previously presented objection to the specification is withdrawn. Applicant on page 8 argues: "The drawings were objected to due to various informalities, which have been addressed in the attached replacement drawings. Specifically, the replacement drawing for FIG. 5 amends the font in the text of the flow diagram to be thicker." In view of the aforementioned amendment, the associated previously presented objection to FIG. 5 is withdrawn. Applicant on page 8 argues: 'With respect to the objection that lead "lines are required for each reference character except for those which indicate the surface or cross section on which they are placed", all references characters in FIGS. 1-4 with respect to this are already associated with lead lines or clearly indicate the surface on which they are placed, and the Office Action does not point out anything specific in FIGS. 1-4 for which Applicant can address. Nonetheless, the replacement drawings for FIGS. 1-4 amend the reference characters to be underlined, except for those associated with lead lines. Therefore, Applicant respectfully requests withdrawal of the drawings objections.' However, as noted by Examiner in the Office Action, MPEP 608.02, section V, states that “[l]ead lines are required for each reference character except for those which indicate the surface or cross section on which they are placed. 'Such a reference character must be underlined to make it clear that a lead line has not been left out by mistake.'" Therefore, Examiner submits that the Office Action sufficiently pointed out something specific in FIGS. 1-4 for which Applicant could address. Nevertheless, in view of the aforementioned new underlining of reference characters, the previously presented objections to FIGS. 1-4 are withdrawn. However, Examiner notes that amended drawings catalyze additional objections. For example, "Opcode 1" and Opcode 2" are newly underlined, leading to a) a lack of clarity regarding whether "1" and "2" are reference characters, and b) if so, a lack of mention in the specification of "1" and "2". Similarly, see "Opcode 1", "Opcode 2", and Opcode 3" in FIG. 3. Examiner recommends, throughout the figures, removing underlines from text and numbers that are not reference characters. Applicant across pages 8-9 argues: ‘Without agreeing to the rejection, Applicant has amended independent claims 1, 11, and 20 to recite receiving "an instruction including a slot corresponding to an execution unit" and executing "the first operation and the second operation in parallel by the execution unit" … Therefore, Applicant respectfully requests withdrawal of the § 112 rejections.’ In view of the aforementioned amendments, the associated previously presented rejections are withdrawn. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEITH E VICARY whose telephone number is (571)270-1314. The examiner can normally be reached Monday to Friday, 9:00 AM to 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at (571)270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KEITH E VICARY/ Primary Examiner, Art Unit 2183
Read full office action

Prosecution Timeline

Show 4 earlier events
Sep 11, 2025
Applicant Interview (Telephonic)
Sep 30, 2025
Response Filed
Oct 16, 2025
Final Rejection mailed — §112
Nov 18, 2025
Interview Requested
Dec 05, 2025
Response after Non-Final Action
Dec 18, 2025
Request for Continued Examination
Jan 06, 2026
Response after Non-Final Action
Apr 23, 2026
Non-Final Rejection mailed — §112 (current)

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Prosecution Projections

3-4
Expected OA Rounds
58%
Grant Probability
99%
With Interview (+41.3%)
3y 11m (~1y 10m remaining)
Median Time to Grant
High
PTA Risk
Based on 684 resolved cases by this examiner. Grant probability derived from career allowance rate.

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