DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this office action and presented for examination. Claims 1, 4, 11, 14, and 20 are newly amended by the response received June 26, 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Asal et al. (Asal) (US 7673119 B2).
Consider claim 1, Asal discloses a system (col. 3, lines 30-31, typical digital signal processor system 100) comprising: one or more processors (col. 3, lines 32-33, central processing unit core 110); and one or more storage devices (for example, FIG. 1, L1I 121, L1D 123, L2 130, External Memory 161) coupled to the one or more processors (col. 3, lines 32-33, central processing unit core 110), the one or more processors configured to: receive an instruction (col. 5, line 19, fetch packets; col. 5, lines 19-20, execute packets; col. 4, line 5, VLIW); determine a first operation (col. 8, line 43, I0 1011) of the instruction (col. 5, line 19, fetch packets; col. 5, lines 19-20, execute packets; col. 4, line 5, VLIW) by extracting a first operation code (col. 6, line 43, opcode; col. 8, line 43, I0 1011) from the instruction (col. 5, line 19, fetch packets; col. 5, lines 19-20, execute packets; col. 4, line 5, VLIW), the first operation (col. 8, line 43, I0 1011) utilizing one or more data paths (col. 4, lines 58-59, four corresponding functional units (L, S, M, and D)) of an execution unit (col. 4, line 58, data path); determine a second operation (col. 8, line 43, I1 1012) of the instruction (col. 5, line 19, fetch packets; col. 5, lines 19-20, execute packets; col. 4, line 5, VLIW) based on the first operation (col. 5, lines 20-21, execute packets consist of one or more instructions which are coded to execute in parallel; col. 9, lines 27-29, a corresponding bit within p bit field 1130 indicates the execute packet for the pair of instructions within the instruction slot; col. 6, lines 63-64, each instruction in an execute packet must use a different functional unit) by extracting a second operation code (col. 6, line 43, opcode; col. 8, line 43, I1 1012) from the instruction (col. 5, line 19, fetch packets; col. 5, lines 19-20, execute packets; col. 4, line 5, VLIW), the second operation (col. 8, line 43, I1 1012) utilizing one or more remaining (col. 6, lines 63-64, each instruction in an execute packet must use a different functional unit) data paths (col. 4, lines 58-59, four corresponding functional units (L, S, M, and D)) of the execution unit (col. 4, line 58, data path), excluding the one or more data paths utilized by the first operation (col. 6, lines 63-64, each instruction in an execute packet must use a different functional unit); assign the first operation (col. 8, line 43, I0 1011) and the second operation (col. 8, line 43, I1 1012) to a slot (col. 8, line 42, instruction slot 1010) corresponding to the execution unit (col. 9, lines 30-33, if the corresponding bit within d bit field 1120 indicates half-length instructions, then a corresponding bit within bit field 1140 indicates the data path for the pair of instructions within the instruction slot) by adding the first operation code (col. 8, line 43, I0 1011; col. 6, line 43, opcode) and the second operation code (col. 8, line 43, I1 1012; col. 6, line 43, opcode) to the slot (col. 8, lines 42-43, instruction slot 1010 includes instructions I0 1011 and I1 1012); and executing the first operation and the second operation in parallel (col. 5, lines 20-21, execute packets consist of one or more instructions which are coded to execute in parallel; col. 9, lines 27-29, a corresponding bit within p bit field 1130 indicates the execute packet for the pair of instructions within the instruction slot) by the execution unit (col. 4, line 58, data path).
Consider claim 2, Asal discloses the system of claim 1 (see above), wherein determining the first operation and determining the second operation further comprise extracting one or more first operands corresponding to the first operation and one or more second operands corresponding to the second operation from the instruction (FIG. 4, creg, z, dst, src2, src1/cst fields).
Consider claim 3, Asal discloses the system of claim 2 (see above), wherein the one or more first operands are independent of the one or more second operands (col. 5, lines 20-21, execute packets consist of one or more instructions which are coded to execute in parallel; for example, two coded instructions coded to execute in parallel would have independent destination operands).
Consider claim 4, Asal discloses the system of claim 1 (see above), wherein assigning the first operation and the second operation to the slot further comprises adding an additional field in the slot for the second operation code (col. 8, lines 42-43, instruction slot 1010 includes instructions I0 1011 and I1 1012; in other words, a field is added in slot 1010 to store I1 1012, relative to slot 1020, for example).
Consider claim 5, Asal discloses the system of claim 1 (see above), wherein the execution unit is an arithmetic logic unit (ALU) (col. 4, line 58, data path; col. 4, lines 58-59, four corresponding functional units (L, S, M, and D); col. 3, lines 37-38, an integer arithmetic logic unit, an integer multiplier; col. 3, line 29, TMS32006400 digital signal processor; for example, col. 5, lines 45-46, multiply instructions).
Consider claim 6, Asal discloses the system of claim 1 (see above), wherein the instruction is a very long instruction word (VLIW) instruction (col. 5, line 19, fetch packets; col. 5, lines 19-20, execute packets; col. 4, line 5, VLIW).
Consider claim 7, Asal discloses the system of claim 1 (see above), wherein determining the second operation is based on a pairing list of operations (col. 1, line 62, product applications; col. 1, line 63, system program).
Consider claim 8, Asal discloses the system of claim 7 (see above), wherein the pairing list of operations comprises a list of primary operations, each primary operation of the list being paired with one or more secondary operations that do not conflict with respective primary operations (col. 6, lines 54-62, the p-bit determines whether the instruction executes in parallel with the following instruction. The p-bits are scanned from lower to higher address. If p=1 for the current instruction, then the next instruction executes in parallel with the current instruction. If p=0 for the current instruction, then the next instruction executes in the cycle after the current instruction).
Consider claim 9, Asal discloses the system of claim 1 (see above), wherein the instruction comprises a plurality of slots (col. 8, lines 40-41, seven instruction slots 1010, 1020, 1030, 1040, 1050, 1060 and 1070) corresponding to respective execution units (col. 9, lines 30-33, if the corresponding bit within d bit field 1120 indicates half-length instructions, then a corresponding bit within bit field 1140 indicates the data path for the pair of instructions within the instruction slot; col. 9, line 23, s bits field 1140).
Consider claim 10, Asal discloses the system of claim 1 (see above), wherein determining the second operation is based on one or more execution conditions of the first operation and the second operation (col. 5, lines 20-21, execute packets consist of one or more instructions which are coded to execute in parallel; col. 9, lines 27-29, a corresponding bit within p bit field 1130 indicates the execute packet for the pair of instructions within the instruction slot; col. 6, lines 63-64, each instruction in an execute packet must use a different functional unit).
Consider claim 11, Asal discloses a method for multi-instruction packing (col. 8, lines 42-43, instruction slot 1010 includes instructions I0 1011 and I1 1012) comprising: receiving, by one or more processors (col. 3, lines 32-33, central processing unit core 110), an instruction (col. 5, line 19, fetch packets; col. 5, lines 19-20, execute packets; col. 4, line 5, VLIW); determining, by the one or more processors, a first operation (col. 8, line 43, I0 1011) by extracting a first operation code (col. 6, line 43, opcode; col. 8, line 43, I0 1011) from the instruction (col. 5, line 19, fetch packets; col. 5, lines 19-20, execute packets; col. 4, line 5, VLIW), the first operation (col. 8, line 43, I0 1011) utilizing one or more data paths (col. 4, lines 58-59, four corresponding functional units (L, S, M, and D)) of an execution unit (col. 4, line 58, data path); determining, by the one or more processors, a second operation (col. 8, line 43, I1 1012) of the instruction (col. 5, line 19, fetch packets; col. 5, lines 19-20, execute packets; col. 4, line 5, VLIW) based on the first operation (col. 5, lines 20-21, execute packets consist of one or more instructions which are coded to execute in parallel; col. 9, lines 27-29, a corresponding bit within p bit field 1130 indicates the execute packet for the pair of instructions within the instruction slot; col. 6, lines 63-64, each instruction in an execute packet must use a different functional unit) by extracting a second operation code (col. 6, line 43, opcode; col. 8, line 43, I1 1012) from the instruction (col. 5, line 19, fetch packets; col. 5, lines 19-20, execute packets; col. 4, line 5, VLIW), the second operation (col. 8, line 43, I1 1012) utilizing one or more remaining (col. 6, lines 63-64, each instruction in an execute packet must use a different functional unit) data paths (col. 4, lines 58-59, four corresponding functional units (L, S, M, and D)) of the execution unit (col. 4, line 58, data path), excluding the one or more data paths utilized by the first operation (col. 6, lines 63-64, each instruction in an execute packet must use a different functional unit); assigning, by the one or more processors, the first operation (col. 8, line 43, I0 1011) and the second operation (col. 8, line 43, I1 1012) to a slot (col. 8, line 42, instruction slot 1010) corresponding to the execution unit (col. 9, lines 30-33, if the corresponding bit within d bit field 1120 indicates half-length instructions, then a corresponding bit within bit field 1140 indicates the data path for the pair of instructions within the instruction slot) by adding the first operation code (col. 8, line 43, I0 1011; col. 6, line 43, opcode) and the second operation code (col. 8, line 43, I1 1012; col. 6, line 43, opcode) to the slot (col. 8, lines 42-43, instruction slot 1010 includes instructions I0 1011 and I1 1012); and executing, by the one or more processors, the first operation and the second operation in parallel (col. 5, lines 20-21, execute packets consist of one or more instructions which are coded to execute in parallel; col. 9, lines 27-29, a corresponding bit within p bit field 1130 indicates the execute packet for the pair of instructions within the instruction slot) by the execution unit (col. 4, line 58, data path).
Consider claim 12, Asal discloses the method of claim 11 (see above), wherein determining the first operation and determining the second operation further comprise extracting one or more first operands corresponding to the first operation and one or more second operands corresponding to the second operation from the instruction (FIG. 4, creg, z, dst, src2, src1/cst fields).
Consider claim 13, Asal discloses the method of claim 12 (see above), wherein the one or more first operands are independent of the one or more second operands (col. 5, lines 20-21, execute packets consist of one or more instructions which are coded to execute in parallel; for example, two coded instructions coded to execute in parallel would have independent destination operands).
Consider claim 14, Asal discloses the method of claim 11 (see above), wherein assigning the first operation and the second operation to the slot further comprises adding an additional field in the slot for the second operation code (col. 8, lines 42-43, instruction slot 1010 includes instructions I0 1011 and I1 1012; in other words, a field is added in slot 1010 to store I1 1012, relative to slot 1020, for example).
Consider claim 15, Asal discloses the method of claim 11 (see above), wherein the execution unit is an arithmetic logic unit (ALU) (col. 4, line 58, data path; col. 4, lines 58-59, four corresponding functional units (L, S, M, and D); col. 3, lines 37-38, an integer arithmetic logic unit, an integer multiplier; col. 3, line 29, TMS32006400 digital signal processor; for example, col. 5, lines 45-46, multiply instructions).
Consider claim 16, Asal discloses the method of claim 11 (see above), wherein the instruction is a very long instruction word (VLIW) instruction (col. 5, line 19, fetch packets; col. 5, lines 19-20, execute packets; col. 4, line 5, VLIW).
Consider claim 17, Asal discloses the method of claim 11 (see above), wherein determining the second operation is based on a pairing list of operations (col. 1, line 62, product applications; col. 1, line 63, system program).
Consider claim 18, Asal discloses the method of claim 17 (see above), wherein the pairing list of operations comprises a list of primary operations, each primary operation of the list being paired with one or more secondary operations that do not conflict with respective primary operations (col. 6, lines 54-62, the p-bit determines whether the instruction executes in parallel with the following instruction. The p-bits are scanned from lower to higher address. If p=1 for the current instruction, then the next instruction executes in parallel with the current instruction. If p=0 for the current instruction, then the next instruction executes in the cycle after the current instruction).
Consider claim 19, Asal discloses the method of claim 11 (see above), wherein determining the second operation is based on one or more execution conditions of the first operation and the second operation (col. 5, lines 20-21, execute packets consist of one or more instructions which are coded to execute in parallel; col. 9, lines 27-29, a corresponding bit within p bit field 1130 indicates the execute packet for the pair of instructions within the instruction slot; col. 6, lines 63-64, each instruction in an execute packet must use a different functional unit).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Asal et al. (Asal) (US 7673119 B2) in view of Hudepohl et al. (Hudepohl) (US 20050038975).
Consider claim 20, Asal discloses one or more processors (col. 3, lines 32-33, central processing unit core 110) to perform operations for multi-instruction packing (col. 8, lines 42-43, instruction slot 1010 includes instructions I0 1011 and I1 1012), the operations comprising: receiving an instruction (col. 5, line 19, fetch packets; col. 5, lines 19-20, execute packets; col. 4, line 5, VLIW); determining a first operation (col. 8, line 43, I0 1011) of the instruction (col. 5, line 19, fetch packets; col. 5, lines 19-20, execute packets; col. 4, line 5, VLIW) by extracting a first operation code (col. 6, line 43, opcode; col. 8, line 43, I0 1011) from the instruction (col. 5, line 19, fetch packets; col. 5, lines 19-20, execute packets; col. 4, line 5, VLIW), the first operation (col. 8, line 43, I0 1011) utilizing one or more data paths (col. 4, lines 58-59, four corresponding functional units (L, S, M, and D)) of an execution unit (col. 4, line 58, data path); determining a second operation (col. 8, line 43, I1 1012) of the instruction (col. 5, line 19, fetch packets; col. 5, lines 19-20, execute packets; col. 4, line 5, VLIW) based on the first operation (col. 5, lines 20-21, execute packets consist of one or more instructions which are coded to execute in parallel; col. 9, lines 27-29, a corresponding bit within p bit field 1130 indicates the execute packet for the pair of instructions within the instruction slot; col. 6, lines 63-64, each instruction in an execute packet must use a different functional unit) by extracting a second operation code (col. 6, line 43, opcode; col. 8, line 43, I1 1012) from the instruction (col. 5, line 19, fetch packets; col. 5, lines 19-20, execute packets; col. 4, line 5, VLIW), the second operation (col. 8, line 43, I1 1012) utilizing one or more remaining (col. 6, lines 63-64, each instruction in an execute packet must use a different functional unit) data paths (col. 4, lines 58-59, four corresponding functional units (L, S, M, and D)) of the execution unit (col. 4, line 58, data path), excluding the one or more data paths utilized by the first operation (col. 6, lines 63-64, each instruction in an execute packet must use a different functional unit); assigning the first operation (col. 8, line 43, I0 1011) and the second operation (col. 8, line 43, I1 1012) to a slot (col. 8, line 42, instruction slot 1010) corresponding to the execution unit (col. 9, lines 30-33, if the corresponding bit within d bit field 1120 indicates half-length instructions, then a corresponding bit within bit field 1140 indicates the data path for the pair of instructions within the instruction slot) by adding the first operation code (col. 8, line 43, I0 1011; col. 6, line 43, opcode) and the second operation code (col. 8, line 43, I1 1012; col. 6, line 43, opcode) to the slot (col. 8, lines 42-43, instruction slot 1010 includes instructions I0 1011 and I1 1012); and executing the first operation and the second operation in parallel (col. 5, lines 20-21, execute packets consist of one or more instructions which are coded to execute in parallel; col. 9, lines 27-29, a corresponding bit within p bit field 1130 indicates the execute packet for the pair of instructions within the instruction slot) by the execution unit (col. 4, line 58, data path).
However, Asal does not disclose a non-transitory computer readable medium for storing instructions that, when executed by the one or more processors, cause the one or more processors to perform the aforementioned operations.
On the other hand, Hudepohl discloses a non-transitory computer readable medium for storing instructions that, when executed by one or more processors, cause the one or more processors to perform operations ([0172], lines 3-10, in addition to implementations of the invention using hardware, the invention can be embodied in software disposed, for example, in a computer usable (e.g., readable) medium configured to store the software (i.e., a computer readable program code). The program code causes the enablement of the functions or fabrication, or both, of the invention disclosed herein; [0172], lines 15-18, the program code can be disposed in any known computer usable medium including semiconductor memory, magnetic disk, optical disc (e.g., CD-ROM, DVD-ROM, etc.)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the method of Asal using a non-transitory computer readable medium for storing instruction, as taught by Hudepohl. This modification merely entails a combination of prior art elements according to known methods to yield predictable results, which is an exemplary rationale that may support a conclusion of obviousness, as per MPEP 2143. In addition, the teaching of Hudepohl increases flexibility.
Response to Arguments
Applicant on page 7 argues: “The drawings were objected to as containing various informalities. Without conceding that there is any merit to the objections, Applicant has attached replacement drawings for FIGS. 1-4, which remove underlines from all text and numbers that are not reference characters. Therefore, Applicant respectfully requests withdrawal of the objections to the drawings.”
In view of the aforementioned replacement drawings, the previously presented objections to the drawings are withdrawn.
Applicant on page 8 argues: “For at least these reasons, Applicant respectfully submits that independent claim 1 complies with the written description requirement. Further, since dependent claims incorporate all the features of their respective base claims, Applicant respectfully submits that pending claims 2-10 comply with the written description requirement for at least the reasons discussed above, as well as on their own merits. Applicant also respectfully submits that independent claims 11 and 20 (and claims 12-19 by their dependencies therefrom) comply with the written description requirement for at least the reasons discussed above, as well as on their own merits. Accordingly, Applicant respectfully requests withdrawal of the § 112 rejections.”
In view of the amendments to the independent claims, the aforementioned previously presented written description rejections are withdrawn.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KEITH E VICARY/Primary Examiner, Art Unit 2183
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