Prosecution Insights
Last updated: October 02, 2026
Application No. 18/660,936

SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL STRUCTURE AND MANUFACTURING METHOD OF VERTICAL CHANNEL STRUCTURE

Non-Final OA §102§103
Filed
May 10, 2024
Priority
Oct 30, 2023 — RE 10-2023-0146989
Examiner
CHEN, YU
Art Unit
Tech Center
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
68%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allowance Rate
738 granted / 1087 resolved
+7.9% vs TC avg
Strong +30% interview lift
Without
With
+29.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
85 currently pending
Career history
1184
Total Applications
across all art units

Statute-Specific Performance

§101
2.3%
-37.7% vs TC avg
§103
46.4%
+6.4% vs TC avg
§102
23.6%
-16.4% vs TC avg
§112
22.4%
-17.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1087 resolved cases

Office Action

§102 §103
DETAILED ACTION Election/Restrictions Applicant’s election with traverse of Group I (claims 1-12), Species I (claims 3-5), Species IA (same TMD material), and Species X (claim 8) in the reply filed on 8/3/2026 and interview held on 8/24/2026 is acknowledged. The traversal is on the ground(s) that there is no serious burden to examine all claims. This is not found persuasive because a serious search and examination burned exist due to the distinct subject matter present in the different invention groups and species requiring searching in different classification area and different search queries pertaining to the distinct species. For example, the specific method step of claim 13 require a separate search and examination directed to the method specific limitations. Moreover, the different channel materials recited in claims 3-5,17 vs claims 6-7,18 also require separate searches directed to the materials. The requirement is still deemed proper and is therefore made FINAL. Applicant alleges claims 1-8 and 10-12 as being encompassed by the elections made. Examiner note claims 6-7 pertains to non-elected Species II. Therefore, claims 6-7, 9 and 13-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention and species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 8/3/2026. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 3-4, 8, and 10-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gardner et al. US 2023/0114024 A1 (Gardner). PNG media_image1.png 589 842 media_image1.png Greyscale In re claim 1, Garnder discloses (e.g. FIG. 1B) a semiconductor device comprising: a substrate 101; a first vertical channel 250A having a sheet shape (see FIG. 5, no specific “sheet shape” dimension claimed that would distinguish over a sheet of channel 250A taught by Gardner), the sheet shape of the first vertical channel 250A extending from the substrate 101 in a first direction perpendicular to a surface of the substrate 101 (250A extends vertically above substrate 101 by a thickness of the layer 250A); a spacer 105 at an end of the first vertical channel 250A in the first direction (dielectric spacer 105 above 250A); and a second vertical channel 250B aligned with the first vertical channel 250A on the spacer 105 (250B above dielectric spacer 105) and having a sheet shape (see FIG. 5, no specific “sheet shape” dimension claimed that would distinguish over a sheet of channel 250B taught by Gardner), the sheet shape of the second vertical channel 250B extending in the first direction (250B extends vertically above substrate 101 by a thickness of the layer 250B). In re claim 3, Gardner discloses (e.g. FIG. 1B) the first vertical channel 250A and the second vertical channel 250B each include a same or different transition metal dichalcogenide (TMD) material (¶ 30). In re claim 4, Gardner discloses (e.g. FIG. 1B) wherein the TMD material in the first vertical channel 250A or the TMD material in the second vertical channel 250B independently includes at least one selected from MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, HfS2, HfSe2, NbSe2, and ReSe2 (¶ 30). In re claim 8, Gardner discloses (e.g. FIG. 1B) wherein the first vertical channel 250A and the second vertical channel 250B have different conductivity types from each other (n-type channels 250A and p-type channels 250B, ¶ 41). In re claim 10, Gardner discloses (e.g. FIG. 1B) further comprising: a first source electrode 215A and a first drain electrode 220A which are electrically connected to the first vertical channel 250A; a first gate electrode 146 (of 235A) facing the first vertical channel 250A with a first gate insulating film 140 arranged therebetween; a second source electrode 215B and a second drain electrode 220B which are electrically connected to the second vertical channel 250B; and a second gate electrode 145 (of 235B) facing the second vertical channel 250B with a second gate insulating film 140 arranged therebetween. In re claim 11, Gardner discloses (e.g. FIG. 1B) further comprising: a vertical channel transistor array including a plurality of first vertical channels 250A and a plurality of second vertical channels 250B arranged in a two-dimensional (2D) manner on a plane perpendicular to the first direction (¶ 8,36,42, any number of transistors can be formed above and beside the transistor structures by repeating the material stack layers). In re claim 12, Gardner discloses (e.g. FIG. 1B) wherein the vertical channel transistor array includes a plurality of vertical channel transistor arrays stacked in the first direction with an isolation layer 105 arranged therebetween (¶ 8,36,42, any number of transistors can be formed above and beside the transistor structures by repeating the material stack layers). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Gardner as applied to claim 1, 3, and 4 above, and further in view of Chung et al. US 2022/0037497 A1 (Chung). In re claim 2, Gardner discloses the claim invention including a dielectric spacer 105 between the first vertical channel 250A and the second vertical channel 250B. Gardner discloses the dielectric material can be silicon dioxide, silicon nitride, or oxides of various metals (¶ 27) and the channel material include HfS2 or ZrS2, (¶ 30). Gardner does not explicitly disclose the dielectric spacer 105 includes an oxide of a material of the first vertical channel. However, Chung discloses a stacked transistor (FIGs. 16A-16C) comprising a bottom channel 204a and a top channel 204b separated by a dielectric spacer 242, wherein the spacer 242 includes hafnium oxide or zirconium oxide as suitable isolation material (¶ 41). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Gardner’s dielectric spacer 105 with hafnium oxide or zirconium oxide as suitable isolation material as taught by Chung. It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960). As such, the spacer 105 (hafnium oxide or zirconium oxide) includes an oxide of a material (HfS2 or ZrS2) of the first vertical channel 250A. In re claim 5, Chung discloses (e.g. FIGs. 16-16C) wherein the spacer 242 includes a transition metal oxide (e.g. hafnium oxide or zirconium oxide, ¶ 41). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Li et al. US 2020/0235098 A1 teaches (FIGs. 2A-2B) a stack of a lower channel 206L and an upper channel 206U separated by dielectric spacer 207U, wherein the channels include slabs of TMD material (¶ 42). Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached on 5712728660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YU CHEN/Primary Examiner, Art Unit 2896 YU CHEN Examiner Art Unit 2896
Read full office action

Prosecution Timeline

May 10, 2024
Application Filed
Aug 27, 2026
Examiner Interview (Telephonic)
Sep 08, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
68%
Grant Probability
98%
With Interview (+29.6%)
2y 10m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1087 resolved cases by this examiner. Grant probability derived from career allowance rate.

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