DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-13, and 16-17 rejected under 35 U.S.C. 103 as being unpatentable over Ho et al. (US 8427844 B2, hereinafter H1), and further in view of Mori et al. (US 20220310546 A1, hereinafter M1).
Regarding independent claim 1, H1 discloses in H1 FIG. 1 and associated text A semiconductor device comprising:
a first semiconductor element (transmitter integrated circuit (IC) 60a);
a second semiconductor element (receiver IC 64a);
an insulating element (coil transducer 10a is an insulating element where, in light of the specification, “insulating element” is interpreted as meaning an electrical component through which there is no direct conductive path between input and output, including, but not limited to transformers and capacitors) electrically connected to the first semiconductor element and the second semiconductor element, and insulating the first semiconductor element and the second semiconductor element from each other (transducer 10a is electrically connected to ICs 60a and 64a and insulate the two via dielectric barrier 22a); and
a sealing resin covering the first semiconductor element, the second semiconductor element, and the insulating element (encapsulating material 80 is epoxy (H1 (23)), which is a resin, and surrounds 10a, 60a, and 64a), wherein the sealing resin includes a first portion covering the first semiconductor element, the second semiconductor element, and the insulating element (encapsulating material 80). H1 does not explicitly disclose the sealing resin includes a second portion constituting an outermost surface of the sealing resin, or the second portion is less prone to a tracking phenomenon than the first portion.
However, in the same field of endeavor, M1 discloses in M1 FIG. 4 and associated text the sealing resin includes a second portion constituting an outermost surface of the sealing resin ((B)-layer is the outer surface of the multi-layer resin sheet comprising an (A)- (corresponding to the first portion) and (B)-layer), and the second portion is less prone to a tracking phenomenon than the first portion ((A)-layer has a filler content of 76%-85% by mass while (B)-layer has a filler content of 80%-90% by mass in the most preferable embodiments of M1 (M1 [0056], [0093]). According to the instant application, when the filler content of the second portion is greater than that of the first portion by percent mass, the second portion is less prone to a tracking phenomenon (Instant application p. 15, lines 14-19). Therefore, M1 anticipates an embodiment in which (B)-layer is inherently less prone to a tracking phenomenon than (A)-layer because the preferred filler content range of (B)-layer is greater than that of (A)-layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the multi-layer resin of M1 and its composition with the semiconductor device of H1 such that M1’s (A)-layer corresponds to H1’s encapsulating material 80 and M1’s (B)-layer is formed on its outermost surface to provide a semiconductor device with warpage of encapsulated components suppressed (M1 [0093]).
Regarding dependent claim 2, H1, as modified by M1, further discloses in M1 FIG. 4 and associated text The semiconductor device according to claim 1, wherein the first portion includes a first resin portion and a plurality of first fillers ((A)-layer contains one or more fillers (M1 [0052])), the second portion includes a second resin portion and a plurality of second fillers ((B)-layer contains fillers (M1 [0092])), and a content percentage of the second fillers in the second portion is higher than a content percentage of the first fillers in the first portion ((A)-layer has a filler content of 76%-85% by mass while (B)-layer has a filler content of 80%-90% by mass in the most preferable embodiments of M1 (M1 [0056], [0093]). Therefore, M1 anticipates an embodiment in which the filler content of (B)-layer is greater than that of (A)-layer).
Regarding dependent claim 3, H1, as modified by M1, further discloses in M1 FIG. 4 and associated text The semiconductor device according to claim 2, wherein the second fillers contain at least one of silicon oxide (SiO2) and alumina (Al2O3) ((B)-layer contains fillers of the same kind as (A)-layer, which may include silica and alumina (M1 [0092], [0052])).
Regarding dependent claim 4, H1, as modified by M1, further discloses in M1 FIG. 4 and associated text The semiconductor device according to claim 2, wherein the first fillers contain at least one of silicon oxide (SiO2) and alumina (Al2O3) ((A)-layer fillers may include silica and alumina (M1 [0092], [0052])).
Regarding dependent claim 5, H1, as modified by M1, further discloses in M1 FIG. 4 and associated text The semiconductor device according to claim 4, wherein the first fillers and the second fillers contain silicon oxide (SiO2) ((B)-layer contains fillers of the same kind as (A)-layer, which may include silica and alumina (M1 [0092], [0052])).
Regarding dependent claim 6, H1, as modified by M1, further discloses in M1 FIG. 4 and associated text The semiconductor device according to claim 1, wherein the second portion contains a low viscosity (LV) resin having a low melting point and a low molecular weight or a dicyclopentadiene (DCPD) resin having an alicyclic structure ((B)-layer contains DCPD glycidyl ether, a DCPD resin (M1 [0097]-[0099]), where DCPD resins are earlier identified as being alicyclic (M1 [0063])).
Regarding dependent claim 8, H1, as modified by M1, further discloses in H1 FIG. 1 and associated text The semiconductor device according to claim 1, further comprising a conductive member electrically connected to the first semiconductor element and the second semiconductor element (lead frames 56 and 58 connected to 60a and 64a respectively), wherein the conductive member includes a first die pad and a second die pad spaced apart from each other (portions of 56 and 58 on which 60a, 64a, and/or 10a attach are interpreted as a first and second die pad; see annotated H1 FIG. 1 below), the first die pad and the second die pad are insulated from each other via the first portion (80 is between and therefore insulating 56 and 58 and their respective die pads), the first semiconductor element is supported by the first die pad, and the second semiconductor element is supported by the second die pad (as interpreted, 60a is mounted on the first die pad of 56 and 64a is mounted on the second die pad of 58).
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Regarding dependent claim 9, H1, as modified by M1, further discloses in H1 FIG. 1 and associated text The semiconductor device according to claim 8, wherein the insulating element is supported by the first die pad (10a is supported by the portion of 56 on which dies are attached, corresponding to the first die pad).
Regarding dependent claim 10, H1, as modified by M1, further discloses in H1 FIG. 1 and associated text The semiconductor device according to claim 8, wherein the insulating element is supported by the first die pad (10a is supported by the portion of 58 on which dies are attached, corresponding to the second die pad).
Regarding dependent claim 11, H1, as modified by M1, further discloses in H1 FIG. 1 and associated text The semiconductor device according to claim 1, further comprising a conductive member electrically connected to the first semiconductor element and the second semiconductor element (lead frames 56 and 58 connected to 60a and 64a respectively, together considered a conductive member), the conductive member includes a die pad (portions of 56 and 58 on which 60a, 64a, and/or 10a attach are together interpreted as a die pad; see annotated H1 FIG. 1 below), and the first semiconductor element, the second semiconductor element, and the insulating element are supported by the die pad (as interpreted, 60a, 64a, and 10a are mounted on the die pad of 56 and 58).
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Regarding dependent claim 12, H1, as modified by M1, further discloses in H1 FIG. 1 and associated text The semiconductor device according to claim 11, wherein the second semiconductor element and the insulating element are supported by the die pad via an insulating substrate (64a and 10a are supported by adhesive tape 25a, 27a, and 29a, considered an insulating substrate because it may be made of an insulating material such as epoxy (H1 (21))).
Regarding dependent claim 13, H1, as modified by M1, further discloses in H1 FIG. 1 and associated text The semiconductor device according to claim 11, wherein the second semiconductor element and the insulating element are supported by the die pad via an insulating substrate (64a and 10a are supported by adhesive tape 23a, 25a, and 27a, considered an insulating substrate because it may be made of an insulating material such as epoxy (H1 (21))).
Regarding dependent claim 16, H1, as modified by M1, further discloses in H1 FIG. 1 and associated text The semiconductor device according to claim 1, wherein the insulating element is located between the first semiconductor element and the second semiconductor element in a first direction (10a is between 60a and 64a in a horizontal direction).
Regarding dependent claim 17, H1, as modified by M1, further discloses in H1 FIG. 1 and associated text The semiconductor device according to claim 1, wherein the insulating element is either of an inductive type or a capacitive type (10a is a transducer (H1 (20)), which is an inductive component).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over H1, and further in view of M1 and Mori et al. (US 20190091907 A1, hereinafter M2).
Regarding dependent claim 7, H1, as modified by M1, discloses The semiconductor device according to claim 1. It does not explicitly disclose the first portion includes an irregular portion, and the second portion is in contact with the irregular portion.
However, in the same field of endeavor, M2 discloses the first portion includes an irregular portion, and the second portion is in contact with the irregular portion (resin member 10, corresponding to the first portion, has a roughened surface 11a, which is in contact with resin member 20, corresponding to the second portion).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the roughened interface of M2 with the semiconductor device of H1, as modified by M1, to provide good adhesion between the first and second portions (M2 [0056]).
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over H1, and further in view of M1 and Haigh et al. (US 20130154071 A1, hereinafter H2).
Regarding dependent claim 14, H1, as modified by M1, discloses The semiconductor device according to claim 8. It does not explicitly disclose a first wire connected to the first semiconductor element and the conductive member; and a second wire connected to the second semiconductor element and the conductive member, wherein the first wire and the second wire are covered with the first portion.
However, in the same field of endeavor, H2 discloses in H2 FIG. 3 and associated text a first wire connected to the first semiconductor element and the conductive member (wire connection 233 between die 205 and pin 202); and a second wire connected to the second semiconductor element and the conductive member (wire connection 219 between die 215 and pin 222), wherein the first wire and the second wire are covered with the first portion (233 and 219 are covered in encapsulant 230, corresponding to the first portion).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the die-to-lead frame wires of H2 with the semiconductor device of H1, as modified by M1, to provide external connections to pins for signal I/O (H1 [0034]).
Regarding dependent claim 15, H1, as modified by M1 and H2, further discloses in H1 FIG. 1 and associated text The semiconductor device according to claim 14, comprising: a third wire connected to the first semiconductor element and the insulating element (wire bond 48a); and a fourth wire connected to the second semiconductor element and the insulating element (wire bond 54a), wherein the third wire and the fourth wire are covered with the first portion (48a and 54a are covered by 80, corresponding to the first portion).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 9929038 B2, pertaining to another solution to a tracking phenomenon in a sealing resin layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571) 272-9559. The examiner can normally be reached Mon - Thu 8:30 am - 6:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EVERETT T RIRIE/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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