DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 29 April 2026 is entered.
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
i. Claims 21, 22, 24, 25 are rejected under 35 U.S.C. 103 as being unpatentable over Jo et al. (2022/0165834; hereinafter Jo) and Chang et al. (2011/0090194; hereinafter Chang) in view of Nakanishi (2020/0012374; this combination of references hereinafter referred to as JCN).
Regarding claim 21, Jo discloses a fingerprint sensor [0005] comprising:
a read-out line (Figures 7, 9, 10: Comprising ROL) extending in a first direction (Y-direction);
a light receiving element (Comprising PD);
a reset transistor (Comprising FT3) to reset a sensor node (Comprising N1);
a reset signal line (Comprising RSL) to control the reset transistor (Comprising FT3); and
a power line (Comprising at least one of VRL, VSSL),
a gate line (Comprising GWL/GL) configured to supply a gate signal (Comprising GW) and extending in a second direction (X-direction) crossing the first direction (Y-direction), wherein
the power line (Comprising at least one of VRL, VSSL) is configured to supply a voltage (Comprising VRST) to the reset transistor (Comprising FT3) or to the light receiving element (Comprising PD).
Jo does not explicitly disclose the sensor wherein the power line overlaps the read-out line to shield the read-out line from at least one signal line of a pixel disposed adjacent to the fingerprint sensor, and wherein the power line is between the read-out line and the gate line.
In the same field of endeavor, Chang discloses display integrated sensing [0009] wherein the power line (Figure 3B: Comprising 108) overlaps the read-out line (Comprising RL.sub.n) to shield the read-out line from at least one signal line of a pixel disposed adjacent to the fingerprint sensor ([0032]: EMI shielding layer carrying electric potential and shields readout line from RC delay produced by display pixel data lines), and wherein the power line (Comprising 108) is between the read-out line (Comprising RL.sub.n) and the gate line (Comprising SL.sub.n).
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the sensor Jo to be modified wherein the power line overlaps the read-out line to shield the read-out line from at least one signal line of a pixel disposed adjacent to the fingerprint sensor, and wherein the power line is between the read-out line and the gate line, in view of the teaching of Chang, to reduce the introduction of RC delay to the readout line.
Jo in view of Chang do not explicitly disclose the sensor wherein the at least one signal line comprises a gate line.
In the same field of endeavor, Nakanishi discloses a touch screen [0002] wherein the at least one signal line comprises a gate line ([0091]: Shielding furnished from influence of the scan line). This is among measures implemented to simplify layer structuring and reduce manufacturing costs [0064].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the sensor of Jo to be modified wherein the at least one signal line comprises a gate line, in view of the teaching of Nakanishi, to reduce manufacturing costs.
Regarding claim 22, JCN discloses the fingerprint sensor of claim 21. Jo discloses the sensor wherein the at least one signal line is a data line (Figures 7, 9, 10: Comprising DL) of the pixel (Comprising SPx1).
Regarding claim 24, JCN discloses the fingerprint sensor of claim 21. Jo discloses the sensor wherein the power line is a low potential power line (Figures 7, 9, 10: Comprising at least one of VRL, VSSL) which couples the low potential to the light receiving element (Comprising PD) and a light emitting element (Comprising ED) of the pixel [0168].
Regarding claim 25, JCN discloses the fingerprint sensor of claim 21. Jo discloses the sensor wherein the power line is a portion of a reset power line (Figures 7, 9, 10: Comprising at least one of VRL, VSSL) coupled to the reset transistor (Comprising FT3), and the reset transistor (Comprising FT3) is coupled to the reset signal line (Comprising RSL).
ii. Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over JCN, as applied to claim 21 above, and further in view of Li et al. (2023/0168760; hereinafter Li).
Regarding claim 23, JCN discloses the fingerprint sensor of claim 21. Jo discloses the sensor wherein: the reset signal line (Figures 7, 9, 10: Comprising RSL) is coupled to the reset transistor (Comprising FT3).
JCN does not explicitly disclose the sensor wherein the power line is disposed on a layer between the reset transistor and the read-out line.
In the same field of endeavor, Li implements a fingerprint sensor wherein the power line (Figures 8, 11: Comprising 20) is disposed on a layer between the reset transistor (Comprising 123) and the read-out line (Comprising 70). This is among measures implemented to improve pixel aperture ratio [0060].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the sensor of Jo to be modified wherein the power line is disposed on a layer between the reset transistor and the read-out line, in view of the teaching of Li, to increase pixel aperture ratio.
Allowable Subject Matter
Claims 1 – 4, 6 – 18, 20 are allowed.
The following is an examiner’s statement of reasons for allowance: the claimed invention is directed toward a fingerprint sensor comprising: a light emitting element disposed on a substrate, a first sensor transistor configured to control a sensing current based on a voltage of a sensor node, a second sensor transistor configured to supply a reset voltage to the sensor node, third sensor transistor and a power line.
i. Regarding Claim 1 the cited prior art fails to singularly or collectively disclose a fingerprint sensor comprising: a read-out line disposed on a substrate and extending in a first direction; a light receiving element disposed on the read-out line; a first sensor transistor configured to control a sensing current based on a voltage of a sensor node that is coupled to a first electrode of the light receiving element; a second sensor transistor configured to supply a reset voltage to the sensor node based on a reset signal; a third sensor transistor electrically connecting a first electrode of the first sensor transistor with the read-out line based on a gate signal; a power line disposed on a layer between the second sensor transistor and the read-out line and extending in the first direction, the power line overlapping the read-out line; a first active layer disposed on the substrate; a first gate layer disposed on the first active layer; a second gate layer disposed on the first gate layer; a third gate layer disposed on the second active layer; a first source metal layer disposed on the third gate layer; a second source metal layer disposed on the first source metal layer, comprising the power line; and a third source metal layer disposed on the second source metal layer, comprising the read-out line.
Thus, claim 1 is allowed.
ii. Claims 2 – 4, 6 – 11 depend from and inherit limitations of claim 1.
Thus, claims 2 – 4, 6 – 11 are allowed.
iii. Regarding Claim 12, the cited prior art fails to singularly or collectively disclose a fingerprint sensor comprising: a light receiving element disposed on a substrate; a first sensor transistor configured to control a sensing current based on a voltage of a sensor node that is coupled to a first electrode of the light receiving element; a second sensor transistor configured to supply a reset voltage to the sensor node based on a reset signal; a third sensor transistor electrically connecting a first electrode of the first transistor with a read-out line based on a gate signal; a first active layer disposed on the substrate and comprising a semiconductor area of the first sensor transistor; a first gate layer disposed on the first active layer and comprising a gate electrode of the first sensor transistor; a second gate layer disposed on the first gate layer; a second active layer disposed on the second gate layer and comprising a semiconductor area of the second sensor transistor; a third gate layer disposed on the second active layer and comprising a gate electrode of the second sensor transistor; a first source metal layer disposed on the third gate layer; a second source metal layer disposed on the first source metal layer and comprising a power line; and a third source metal layer disposed on the second source metal layer and comprising the read-out line overlapped with the power line.
Thus, claim 12 is allowed.
iv. Claims 13 – 17 depend from and inherit limitation of claim 12.
Thus, claims 13 – 17 are allowed.
v. Regarding Claim 18, the cited prior art fails to singularly or collectively disclose a display device comprising: a read-out line disposed on a substrate and extended in a first direction; a fingerprint sensor disposed on the read-out line and comprising a light receiving element; and a pixel including a light emitting element disposed on a same layer as the light receiving element, wherein the fingerprint sensor further comprising: a first sensor transistor configured to control a sensing current based on a voltage of a sensor node that is a first electrode of the light receiving element; a second sensor transistor configured to supply a reset voltage to the sensor node based on a reset signal; a third sensor transistor electrically connecting a first electrode of the first sensor transistor with the read-out line based on a gate signal; a power line disposed on a layer between the second sensor transistor and the read-out line and extending in the first direction and overlapping the read-out line; a first active layer disposed on the substrate; a first gate layer disposed on the first active layer; a second gate layer disposed on the first gate layer;
a second active layer disposed on the second gate layer; a third gate layer disposed on the second active layer; a first source metal layer disposed on the third gate layer; a second source metal layer disposed on the first source metal layer, comprising the power line; and a third source metal layer disposed on the second source metal layer, comprising the read-out line.
Thus, claim 18 is allowed.
vi. Claim 20 depends from and inherits limitations of claim 18.
Thus, claim 20 is allowed.
---
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Inquiries
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Aaron Midkiff whose telephone number is (571)270-5875. The examiner can normally be reached Monday - Friday, 8:00am - 4:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached at (571)272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AARON MIDKIFF/
Examiner, Art Unit 2621
/AMR A AWAD/Supervisory Patent Examiner, Art Unit 2621
1 x = positive, nonzero integer value labeling respective ones of example sub-pixels.
Prosecution Insights