DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application. Claims 11-20 are amended.
Election/Restrictions
Applicant’s election without traverse of Group I: claims 1-10 and amended claims 11-20 in the reply filed on 18 June 2026 is acknowledged.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement(s) (IDS), Form PTO-1449, filed 17 October 2025. The information therein was considered.
Product-by-Process Limitations
MPEP § 2113 "[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lien et al. (US 6,262907) (hereinafter, “Lien”).
Re: independent claim 1, Lien discloses in fig. 5D a memory device, comprising: a memory cell having a first transistor (501), a second transistor (502), a first capacitor (506) and a second capacitor (507) coupled with each other into a data storage circuit configured to store a datum, and a third transistor (503) and a fourth transistor (504) coupled with each other into a comparison circuit configured to perform a comparison of the datum stored in the data storage circuit with a search input datum and a back-end-of-line (BEOL) structure, wherein the BEOL structure comprises at least a part of the memory cell (BEOL is a product-by-process limitation, see MPEP § 2113. BEOL structure is interpreted as “structure”).
Re: claim 2, Lien discloses in fig. 5D the memory device of claim 1, wherein the BEOL structure comprises an entirety of the memory cell (fig. 5A) (BEOL is a product-by-process limitation, see MPEP § 2113).
Re: claim 3, Lien discloses in fig. 5D the memory device of claim 1, further comprising: a match line (516, 517); a first bit line (520); and a second bit line (521), wherein the third transistor (503) comprises: a first source/drain coupled to the match line (503 is coupled to match lines 516, 517 through 505), and a second source/drain coupled to the first bit line (520), and the fourth transistor (504) comprises: a first source/drain coupled to the match line (504 is coupled to match lines 516, 517 through 505), and a second source/drain coupled to the second bit line (521).
Re: claim 4, Lien discloses in fig. 5D the memory device of claim 3, wherein the data storage circuit comprises: a first node (NA) configured to store a first logic state corresponding to the datum, and a second node (NB) configured to store a second logic state corresponding to the datum and different from the first logic state, the third transistor (503) further comprises a gate coupled to the first node (NA), and the fourth transistor (504) further comprises a gate coupled to the second node (NB).
Claim(s) 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Stephens, Jr. (US 8,559,258).
Re: independent claim 11, Stephens, Jr. discloses in fig. 25 a memory device, comprising: a substrate; front-end-of-line (FEOL) circuitry (102) over the substrate; and back-end-of-line (BEOL) structure (CAM-0 - CAM-7) over the FEOL circuitry and the substrate, wherein the BEOL structure comprises a content-addressable memory (CAM) array (fig. 25) (FEOL and BEOL are product-by-process limitations, see MPEP § 2113. FEOL circuitry is interpreted as “circuitry” and BEOL structure is interpreted as “structure”.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lien et al. (US 6,262907) (hereinafter, “Lien”) in view of Stephens, Jr. (US 8,559,258).
Re: independent claim 19, Lien discloses in fig. 5A a memory device, comprising: a memory cell comprising: first and second capacitors (506, 507), first through fourth transistors (501-504), a first interconnect structure coupling a gate of the third transistor (503) to a source/drain (NA) of the first transistor (501) and the first capacitor (506), and a second interconnect structure coupling a gate of the fourth transistor (504) to a source/drain (NB) of the second transistor (502) and the second capacitor (507).
Lien does not disclose a substrate; front-end-of-line (FEOL) circuitry over a substrate; and a back-end-of-line (BEOL) structure over the FEOL circuitry (BEOL and FEOL are product-by-process limitations, see MPEP § 2113. FEOL circuitry is interpreted as “circuitry” and BEOL structure is interpreted as “structure”.).
Stephens, Jr. discloses in fig. 25 FEOL circuitry (102) over a substrate, a BEOL structure (CAM-0 - CAM-7) over the FEOL circuitry, wherein the BEOL structure comprises a memory cell (CAM-0 - CAM-7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include (FEOL) circuitry over a substrate and a (BEOL) structure including a memory cell over the (FEOL) circuitry for the purpose of reducing the footprint of the memory device as exemplified by Stephens, Jr..
Allowable Subject Matter
Claims 5-10, 12-18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chu et al. US 2011/0051484 teach a dynamic content addressable memory cell.
Doornbos US 2025/0054546 teaches ternary content addressable memory cells formed within a BEOL level.
Huang et al. US 2025/0331144 teach content addressable memory cells including a BEOL layer that is disposed over a FEOL layer.
The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 8/4/2026
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