DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/10/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 7-10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Schaeffer et al. US 2020/0013859 in view of Arai US 2009/0233419.
Re claim 1, Schaeffer teaches a method, comprising:
providing a semiconductor wafer (700, fig3B or 9A, [119]) comprising a plurality of die sites (650, fig3B or 9A, [122]) each including a vertical power semiconductor device (fig2A or 9A, [124]), the semiconductor wafer having a thickness of 250 microns or less (th1 at most 70µm, fig2A or 9A, [119]);
attaching a metallic wafer (800, fig3A or 9C, [131]) to the semiconductor wafer (700, fig3B or 9C).
Schaeffer does not explicitly show the metallic wafer having a similar shape as the semiconductor wafer.
Arai teaches the metallic wafer (3, fig5A, [29]) having a similar shape as the semiconductor wafer (2, fig5A, [29]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Schaeffer and Arai to adjust the shape of the metallic wafer to have a similar shape as the semiconductor wafer. The motivation to do so is to achieve good alignment between the two bonded wafers (Arai, [34]).
Schaeffer modified above teaches before (Schaeffer, fig9B-9C) or after (Schaeffer, fig3C) attaching the metallic wafer to the semiconductor wafer, singulating the die sites into individual semiconductor dies (Schaeffer, dicing along 660, fig3C or 9B, [139]); and
after attaching the metallic wafer to the semiconductor wafer (Schaeffer, fig3B) but before removing the individual semiconductor dies from the semiconductor wafer (Schaeffer, fig3B), singulating the metallic wafer into a plurality of separate metallic bodies (Schaeffer, 810, fig3C, [140]) that remain attached to the individual semiconductor dies (Schaeffer, 650, fig3C, [139]).
Re claim 2, Schaeffer modified above teaches the method of claim 1, wherein attaching the metallic wafer (Schaeffer, 800, fig3B, [131]) to the semiconductor wafer (Schaeffer, 700, fig3B, [119]) comprises attaching a first contact surface (Schaeffer, 801, fig3C, [131]) of a first metallic body (Schaeffer, 810, fig3C, [131]) of the metallic wafer to a first load terminal of the vertical power semiconductor device (Schaeffer, 620, fig3C, [128]) of each die site such that a second contact surface (Schaeffer, 812, fig3C) opposite the first contact surface of each first metallic body forms a contact (Schaeffer, contact with 972, fig12, [200]) for the first load terminal of the vertical power semiconductor device attached to the first metallic body.
Re claim 3, Schaeffer modified above teaches the method of claim 2, wherein the first load terminal of the vertical power semiconductor device of each die site is one of a source terminal, an emitter terminal, a drain terminal (Schaeffer, 620 connected to 972 as drain, fig12, [201]), or a collector terminal.
Re claim 7, Schaeffer modified above teaches the method of claim 1, wherein, before singulating the metallic wafer into a plurality of separate metallic bodies that remain attached to the individual semiconductor dies (Schaeffer, fig3B), the metallic wafer is a solid metallic piece comprising a plurality of distinct metallic bodies (Schaeffer, 810, fig3B, [131]) formed in the solid metallic piece (Schaeffer, 810 on 819, fig3B, [136]).
Re claim 8, Schaeffer modified above teaches the method of claim 1, wherein, before singulating the metallic wafer into a plurality of separate metallic bodies that remain attached to the individual semiconductor dies (Schaeffer, fig3B), the metallic wafer comprises a plurality of distinct metallic bodies interconnected via a web framework (Schaeffer, 810 on 819, fig3B, [136]).
Re claim 9, Schaeffer modified above teaches the method of claim 1, wherein attaching the metallic wafer to the semiconductor wafer comprises at least one of sintering (Schaeffer, fig3B, [129]), diffusion soldering (Schaeffer, fig3B, [129]), or soldering (Schaeffer, fig3B, [129]).
Re claim 10, Schaeffer modified above teaches the method of claim 1, wherein the die sites are at least partially singulated into individual semiconductor dies (Schaeffer, fig9B) before attaching the metallic wafer to the semiconductor wafer (Schaeffer, fig9C).
Re claim 12, Schaeffer modified above teaches the method of claim 1, wherein singulating the die sites into individual semiconductor dies and singulating the metallic wafer into a plurality of separate metallic bodies that remain attached to the individual semiconductor dies are done simultaneously during a same singulation process (Schaeffer, with combined sawing process cut through both 600 and 819, fig3B, [140]).
Claim(s) 4-5, 11, 16-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Schaeffer et al. US 2020/0013859 in view of Arai US 2009/0233419 and Beer et al. US 2015/0061100.
Re claim 4, Schaeffer does not explicitly show the method of claim 2, wherein attaching the metallic wafer to the semiconductor wafer further comprises attaching a first contact surface of a second metallic body of the metallic wafer to a control terminal of the vertical power semiconductor device of each die site such that a second contact surface opposite the first contact surface of each second metallic body forms a contact for the control terminal of the vertical power semiconductor device attached to the second metallic body.
Beer teaches wherein attaching the metallic wafer (21 and 23, fig2, [71]) to the semiconductor wafer (10, fig2, [68]) further comprises attaching a first contact surface (bottom surface of 23 facing 10, fig2) of a second metallic body (23, fig2, [71]) of the metallic wafer (wafer with 21 and 23, fig2) to a control terminal (13, fig2, [71]) of the vertical power semiconductor device of each die site (fig2) such that a second contact surface (top surface of 23, fig2) opposite the first contact surface (bottom surface of 23 facing 10, fig2) of each second metallic body (23, fig2, [71]) forms a contact for the control terminal (13, fig2, [71]) of the vertical power semiconductor device attached to the second metallic body.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Schaeffer, Arai and Beer to adjust the shape of the top and bottom metallic wafer to have a similar shape as the semiconductor wafer and bond both top and bottom contacts as in Beer fig2. The motivation to do so is to achieve good alignment between the two bonded wafers (Arai, [34]) and protect the power device during process (Beer, [7, 70]).
Re claim 5, Schaeffer modified above teaches the method of claim 4, wherein the first load terminal of the vertical power semiconductor device of each die site is a source terminal (Beer, 11 connected with 21, fig2, [5]) or emitter terminal, and wherein the control terminal of the vertical power semiconductor device of each die site is a gate terminal (Beer, 13 connected with 23, fig2, [5]).
Re claim 11, Schaeffer does not explicitly show the method of claim 1, further comprising: after attaching the metallic wafer to the semiconductor wafer but before removing the individual semiconductor dies from the semiconductor wafer, applying an encapsulant that encapsulates at least a part of each die site.
Beer teaches after attaching the metallic wafer (21, 22 and 23, fig1 and 2, [71]) to the semiconductor wafer (10, fig2, [68]) but before removing the individual semiconductor dies from the semiconductor wafer (fig9), applying an encapsulant (4, fig9, [81]) that encapsulates at least a part of each die site.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Schaeffer, Arai and Beer to adjust the shape of the metallic wafer to have a similar shape as the semiconductor wafer and bond both top and bottom contacts with top surface exposed from encapsulant as in Beer. The motivation to do so is to achieve good alignment between the two bonded wafers (Arai, [34]) and protect the power device during process (Beer, [7, 70]).
Re claim 16, Schaeffer modified above teaches the method of claim 1, wherein attaching a metallic wafer to the semiconductor wafer comprises attaching a first metallic wafer to a first side of the semiconductor wafer (Schaeffer, 800 bond to bottom side of 700, fig3B), wherein singulating the metallic wafer into a plurality of separate metallic bodies that remain attached to the individual semiconductor dies comprises singulating the first metallic wafer into a plurality of separate first metallic bodies that remain attached to the individual semiconductor dies (Schaeffer, dicing along 660, fig3C, [139]), and
Schaeffer does not explicitly show wherein the method further comprises: attaching a second metallic wafer to a second, opposite side of the semiconductor wafer, the second metallic wafer having a similar shape as the semiconductor wafer and the first metallic wafer; and after attaching the second metallic wafer to the second side of the semiconductor wafer but before removing the individual semiconductor dies from the semiconductor wafer, singulating the second metallic wafer into a plurality of separate second metallic bodies that remain attached to the individual semiconductor dies.
Beer teaches attaching a second metallic wafer (21 and 23, fig2, [71]) to a second, opposite side of the semiconductor wafer (top side of 10, fig2, [68]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Schaeffer, Arai and Beer to adjust the shape of the metallic wafer to have a similar shape as the semiconductor wafer and bond both top and bottom contacts with top surface exposed from encapsulant as in Beer. The motivation to do so is to achieve good alignment between the two bonded wafers (Arai, [34]) and protect the power device during process (Beer, [7, 70]).
Schaeffer modified above teaches the second metallic wafer having a similar shape as the semiconductor wafer and the first metallic wafer (wafer with 21/23, wafer with 10 and wafer with 22 adjusted to have similar shape to achieve better alignment); and after attaching the second metallic wafer to the second side of the semiconductor wafer but before removing the individual semiconductor dies from the semiconductor wafer (Beer, fig10), singulating the second metallic wafer into a plurality of separate second metallic bodies that remain attached to the individual semiconductor dies (Schaeffer, fig 3C and 12).
Re claim 17, Schaeffer modified above teaches the method of claim 16, wherein attaching the second metallic wafer (Beer, 21 and 23, fig2, [71]) to the second side of the semiconductor wafer (top side of 10, fig2, [68]) comprises attaching a first contact surface of a second metallic body (Beer, bottom surface of 21 or 23, fig2) of the second metallic wafer to a second load terminal of the vertical power semiconductor device (Beer, 11 or 13, fig2) of each die site such that a second contact surface (Beer, top surface of 21 or 23, fig2 and 11) opposite the first contact surface of each second metallic body forms a contact for the second load terminal of the vertical power semiconductor device attached to the second metallic body (Beer, fig11).
Re claim 18, Schaeffer modified above teaches the method of claim 17, wherein the second load terminal of the vertical power semiconductor device of each die site is one of a source terminal (Beer, 11 connected with 21, fig2, [5]), an emitter terminal, a drain terminal, or a collector terminal.
Re claim 20, Schaeffer modified above teaches the method of claim 16, wherein attaching the second metallic wafer to the second side of the semiconductor wafer comprises at least one of sintering (Beer, 31 and 32, fig2, [76]), diffusion soldering (Beer, 31 and 32, fig2, [73]), or soldering (Beer, 31 and 32, fig2, [73]).
Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over Schaeffer et al. US 2020/0013859 in view of Arai US 2009/0233419 and Nakamura US 2024/0096704.
Re claim 13, Schaeffer does not explicitly show the method of claim 1, further comprising: after singulating the die sites into individual semiconductor dies and after singulating the metallic wafer into a plurality of separate metallic bodies that remain attached to the individual semiconductor dies, picking one or more of the individual semiconductor dies by contacting a metallic body attached to a respective individual semiconductor die with a component of a pick and place machine and removing the respective individual semiconductor die from the semiconductor wafer.
Nakamura teaches picking one or more of the individual semiconductor dies (12’, fig9B) by contacting top surface of individual semiconductor die with a component of a pick and place machine (64, fig9B, [47]) and removing the respective individual semiconductor die from the semiconductor wafer (wafer with 12, fig9B).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Schaeffer modified above and Nakamura to use a pick in contact with back side of chip with bonded metallic layer. The motivation to do so is to prevent scratches forming during bonding process (Nakamura, [6]).
Schaeffer modified above teaches the method of claim 1, further comprising: after singulating the die sites into individual semiconductor dies (Arai 22 in fig7B as Schaeffer 650 in fig3C) and after singulating the metallic wafer into a plurality of separate metallic bodies (Arai 30 in fig7B as Schaeffer 810 in fig3C) that remain attached to the individual semiconductor dies (Arai, fig7B), picking one or more of the individual semiconductor dies by contacting a metallic body attached to a respective individual semiconductor die with a component of a pick and place machine and removing the respective individual semiconductor die from the semiconductor wafer (Nakamura pick 64 in fig9B used to contact top surface of metal layer 30 in Arai fig7B on tape 6).
Claim(s) 14-15 and 21-23 is rejected under 35 U.S.C. 103 as being unpatentable over Schaeffer et al. US 2020/0013859 in view of Arai US 2009/0233419, Nakamura US 2024/0096704 and Beer et al. US 2015/0061100.
Re claim 14, Schaeffer does not explicitly show the method of claim 13, further comprising: after removing the respective individual semiconductor die from the semiconductor wafer, placing, with the pick and place machine, the respective individual semiconductor die on a power semiconductor module.
Schaeffer teaches place the respective individual semiconductor die on a power semiconductor module (fig12).
Beer teaches after attaching the metallic wafers (21, 22 and 23, fig1 and 2, [71]) to the semiconductor wafer (10, fig2, [68]) but before removing the individual semiconductor dies from the semiconductor wafer (fig9), applying an encapsulant (4, fig9, [81]) that encapsulates at least a part of each die site.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Schaeffer, Arai and Beer to adjust the shape of the metallic wafer to have a similar shape as the semiconductor wafer and bond both top and bottom contacts with top surface exposed from encapsulant as in Beer. The motivation to do so is to achieve good alignment between the two bonded wafers (Arai, [34]) and protect the power device during process (Beer, [7, 70]).
Nakamura teaches picking one or more of the individual semiconductor dies (12’, fig9B) by contacting top surface of individual semiconductor die with a component of a pick and place machine (64, fig9B, [47]) and removing the respective individual semiconductor die from the semiconductor wafer (wafer with 12, fig9B).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Schaeffer modified above and Nakamura to use a pick in contact with front side of chip with bonded metallic layer and place on drain terminal 972 of Schaeffer in fig12 with a pick and place machine 64 as in Nakamura fig9B. The motivation to do so is to prevent scratches forming during bonding process (Nakamura, [6]).
Re claim 15, Schaeffer modified above teaches the method of claim 14, wherein placing the respective individual semiconductor on the power semiconductor module comprises attaching the respective individual semiconductor die to the power semiconductor module by diffusion soldering, soldering (Schaeffer, 320 soldered on 7-972, fig12, [200]), or sintering.
Re claim 21, Schaeffer modified above teaches the method of claim 16, further comprising: after singulating the die sites into individual semiconductor dies, after singulating the first metallic wafer into a plurality of separate first metallic bodies, and after singulating the second metallic wafer into a plurality of separate second metallic bodies and removing the respective individual semiconductor die from the semiconductor wafer (bond top metallic wafer with 21/23 and bottom metallic wafer with 22 as in fig2 of Beer followed by dicing and placing as in Schaeffer 12).
Schaeffer does not explicitly show picking one or more of the individual semiconductor dies by contacting the first metallic body or the second metallic body attached to a respective individual semiconductor die with a component of a pick and place machine and removing the respective individual semiconductor die from the semiconductor wafer.
Nakamura teaches picking one or more of the individual semiconductor dies (12’, fig9B) by contacting top surface of individual semiconductor die with a component of a pick and place machine (64, fig9B, [47]) and removing the respective individual semiconductor die from the semiconductor wafer (wafer with 12, fig9B).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Schaeffer modified above and Nakamura to use a pick in contact with front side of chip with bonded metallic layer and place on drain terminal 972 of Schaeffer in fig12 with a pick and place machine 64 as in Nakamura fig9B. The motivation to do so is to prevent scratches forming during bonding process (Nakamura, [6]).
Re claim 22, Schaeffer modified above teaches the method of claim 21, further comprising: after removing the respective individual semiconductor die from the semiconductor wafer, placing, with the pick and place machine (Nakamura, 64, fig9B), the respective individual semiconductor die on a semiconductor module (Schaeffer, 320 soldered on 7-972, fig12, [200]).
Re claim 23, Schaeffer modified above teaches the method of claim 22, wherein placing the respective individual semiconductor on the semiconductor module comprises attaching the respective individual semiconductor die to the semiconductor module by diffusion soldering, soldering (Schaeffer, 320 soldered on 7-972, fig12, [200]), or sintering.
Allowable Subject Matter
Claim 6 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
Specifically, the limitations are material to the inventive concept of the application in hand to reducing the risk of damage to the die during handling of the dies by attaching the metallic bodies to the thin semiconductor dies.
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812
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