DETAILED ACTION
1. This is in response to the application No. 18/661,060 filed on 05/10/2024. Claims 1-20 are submitted for examination. Claims 1, 16 and 18 are independent.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
3. This application filed on 05/10/2024 is a Continuation of 17199438, filed 03/12/2021, now U.S. Patent # 12001593 claims foreign priority to 2002929, filed on 03/25/2020.
Information Disclosure Statement
4. The information disclosure statements (IDS) submitted on 05/10/2024, 08/01/2025 and 08/06/2025 have been considered. The submission is in-compliance with the provisions of 37 CFR 1.97. Form PTO-1449 is signed and attached hereto.
Drawings
5. The drawings filed on May 10, 2024 are accepted.
Specification
6. The specification filed on May 10, 2024 is also accepted.
Double Patenting
7. The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
8. Claims 1-20 are rejected under judicially created doctrine of obviousness-type double patenting on the ground of non-statutory double patenting as being unpatentable over claims 1-20 of Patent No. 12/001,593 B2 (herein after referred as ‘593 patent)
Although the claims at issue are not identical, they are not patentably distinct from each other because they recite the same limitations and only differ by statutory category of invention. It would have been obvious to a person having ordinary skill in the art at the time the invention was made to have implemented the invention as any of a method, system or computer program product.
The following is referring to the independent claims 1, 16 and 18:
[Symbol font/0xB7] Independent claim 1 of the instant application and independent claim 1 and dependent claim 8, of the ‘593 patent recite similar limitation. The above claims, namely claim 1 of the instant/present application would have been obvious over claims 1 and 8, of the ‘593 patent, because every element of the above independent claim 1 of the present application is anticipated by the corresponding claims 1 and 8 of the ‘593 patent
[Symbol font/0xB7] Independent claim 16 of the instant application and independent claim 19, of the ‘593 patent recite similar limitation. The above claims, namely claim 19 of the instant/present application would have been obvious over claim 16 of the ‘593 patent, because every element of the above independent claim 16 of the present application is anticipated by the corresponding claim 19 of the ‘593 patent
[Symbol font/0xB7] Independent claim 18 of the instant application and independent claim 16, of the ‘593 patent recite similar limitation. The above claims, namely claim 18 of the instant/present application would have been obvious over claim 16, of the ‘593 patent, because every element of the above independent claim 18 of the present application is anticipated by the corresponding claim 16 of the ‘548 patent
The following is referring to the dependent claims 2-15, 17 and 19-20
[Symbol font/0xB7] Dependent claim 2 of the instant application and dependent claim 2, of the ‘593 patent recite similar limitation. The above claims, namely claims 2 of the instant/present application would have been obvious over claim 2, of the ‘593 patent, because every element of the above dependent claim 2 of the present application is anticipated by the corresponding claim 2 of the ‘593 patent.
[Symbol font/0xB7] Dependent claim 3 of the instant application and dependent claim 3, of the ‘593 patent recite similar limitation. The above claims, namely claims 3 of the instant/present application would have been obvious over claim 3, of the ‘593 patent, because every element of the above dependent claim 3 of the present application is anticipated by the corresponding claim 3 of the ‘593 patent.
[Symbol font/0xB7] Dependent claim 4 of the instant application and dependent claim 4, of the ‘593 patent recite similar limitation. The above claims, namely claim 4 of the instant/present application would have been obvious over claim 4, of the ‘593 patent, because every element of the above dependent claim 4 of the present application is anticipated by the corresponding claim 4 of the ‘593 patent
[Symbol font/0xB7] Dependent claim 5 of the instant application and dependent claim 5, of the ‘593 patent recite similar limitation. The above claims, namely claim 5 of the instant/present application would have been obvious over claim 5, of the ‘593 patent, because every element of the above dependent claim 5 of the present application is anticipated by the corresponding claim 5 of the ‘593 patent.
[Symbol font/0xB7] Dependent claim 6 of the instant application and dependent claim 6, of the ‘593 patent recite similar limitation. The above claims, namely claim 6 of the instant/present application would have been obvious over claim 6, of the ‘593 patent, because every element of the above dependent claim 6 of the present application is anticipated by the corresponding claim 6 of the ‘593 patent.
[Symbol font/0xB7] Dependent claim 7 of the instant application and dependent claim 7, of the ‘593 patent recite similar limitation. The above claims, namely claim 7 of the instant/present application would have been obvious over claim 7, of the ‘593 patent, because every element of the above dependent claim 7 of the present application is anticipated by the corresponding claim 7 of the ‘593 patent.
[Symbol font/0xB7] Dependent claim 8 of the instant application and dependent claim 8, of the ‘593 patent recite similar limitation. The above claims, namely claim 8 of the instant/present application would have been obvious over claim 8, of the ‘593 patent, because every element of the above dependent claim 8 of the present application is anticipated by the corresponding claim 8 of the ‘593 patent.
[Symbol font/0xB7] Dependent claim 9 of the instant application and dependent claim 9, of the ‘593 patent recite similar limitation. The above claims, namely claim 9 of the instant/present application would have been obvious over claim 9, of the ‘593 patent, because every element of the above dependent claim 9 of the present application is anticipated by the corresponding claim 9 of the ‘593 patent.
[Symbol font/0xB7] Dependent claim 10 of the instant application and dependent claim 10, of the ‘593 patent recite similar limitation. The above claims, namely claim 10 of the instant/present application would have been obvious over claim 10, of the ‘593 patent, because every element of the above dependent claim 10 of the present application is anticipated by the corresponding claim 10 of the ‘593 patent.
[Symbol font/0xB7] Dependent claim 11 of the instant application and dependent claim 11, of the ‘593 patent recite similar limitation. The above claims, namely claim 11 of the instant/present application would have been obvious over claim 11, of the ‘593 patent, because every element of the above dependent claim 11 of the present application is anticipated by the corresponding claim 11 of the ‘593 patent.
[Symbol font/0xB7] Dependent claim 12 of the instant application and dependent claim 12, of the ‘593 patent recite similar limitation. The above claims, namely claim 12 of the instant/present application would have been obvious over claim 12, of the ‘593 patent, because every element of the above dependent claim 12 of the present application is anticipated by the corresponding claim 12 of the ‘593 patent.
[Symbol font/0xB7] Dependent claim 13 of the instant application and dependent claim 13, of the ‘593 patent recite similar limitation. The above claims, namely claim 13 of the instant/present application would have been obvious over claim 13, of the ‘593 patent, because every element of the above dependent claim 13 of the present application is anticipated by the corresponding claim 6613 of the ‘593 patent
[Symbol font/0xB7] Dependent claim 14 of the instant application and dependent claim 14, of the ‘593 patent recite similar limitation. The above claims, namely claim 14 of the instant/present application would have been obvious over claim 14, of the ‘593 patent, because every element of the above dependent claim 14 of the present application is anticipated by the corresponding claim 14 of the ‘593 patent.
[Symbol font/0xB7] Dependent claim 15 of the instant application and dependent claim 15, of the ‘593 patent recite similar limitation. The above claims, namely claim 15 of the instant/present application would have been obvious over claim 15, of the ‘593 patent, because every element of the above dependent claim 15 of the present application is anticipated by the corresponding claim 15 of the ‘593 patent.
[Symbol font/0xB7] Dependent claim 17 of the instant application and dependent claim 3, of the ‘593 patent recite similar limitation. The above claims, namely claim 17 of the instant/present application would have been obvious over claim 3, of the ‘593 patent, because every element of the above dependent claim 17 of the present application is anticipated by the corresponding claim 3 of the ‘593 patent.
[Symbol font/0xB7] Dependent claim 19 of the instant application and dependent claim 2, of the ‘593 patent recite similar limitation. The above claims, namely claim 19 of the instant/present application would have been obvious over claim 2, of the ‘593 patent, because every element of the above dependent claim 19 of the present application is anticipated by the corresponding claim 2 of the ‘593 patent.
Examiner Note: The following table maps claims 1-20 of the instant application with the corresponding claims of the ‘593 patent.
Instant Application: Application No. 18/661,060
US Patent No. ‘593 Patent
1, 16 and 18. A system comprising:
a physical unclonable function device, the device comprising:
a first assembly of non-volatile memory cells each having a selection transistor embedded in a semiconductor substrate and a depletion-type state transistor having a control gate and a floating gate that are electrically connected, the state transistors having respective effective threshold voltages belonging to a common random distribution; and
a processing circuit configured to deliver, to an output interface of the device, a group of output data, wherein the output data is based on readings of the effective threshold voltages of the state transistors of the memory cells of the first assembly, and is based on corresponding reliability information corresponding with the state transistors of the memory cells of the first assembly.
1. A system comprising:
a physical unclonable function device, the device comprising:
a first assembly of non-volatile memory cells each having a selection transistor embedded in a semiconductor substrate and a depletion-type state transistor having a control gate and a floating gate that are electrically connected, the depletion-type state transistors having respective effective threshold voltages belonging to a common random distribution; and
a processing circuit configured to deliver, to an output interface of the device, a group of output data based on differential readings of pairs of effective threshold voltages of the depletion-type state transistors of pairs of the memory cells of the first assembly.
8. wherein the processing circuit includes a first generating circuit configured to generate the reliability information in accordance with a margin value on the differential readings of the effective threshold voltages of the depletion-type state transistors of the pairs of symmetric memory cells.
2. The system according to claim 1, wherein each memory cell includes a gate oxide disposed between the floating gate of the depletion-type state transistor and the substrate, a thickness of the gate oxide being greater than 8 nanometers.
2. The system according to claim 1, wherein each memory cell includes a gate oxide disposed between the floating gate of the depletion-type state transistor and the substrate, a thickness of the gate oxide being greater than 8 nanometers.
3. The system according to claim 1, wherein:
the processing circuit includes a reading circuit configured to carry out the readings;
the first assembly of non-volatile memory cells is organized into two first matrix sub-assemblies disposed symmetrically with respect to the reading circuit, all rows of the two first matrix sub-assemblies being parallel; and
the reading circuit is configured to carry out differential readings of pairs of effective threshold voltages of the depletion-type state transistors of pairs of symmetric memory cells located respectively in the two first matrix sub-assemblies on homologous columns of the two first matrix sub-assemblies.
3. The system according to claim 1, wherein:
the processing circuit includes a reading circuit configured to carry out the differential readings;
the first assembly of non-volatile memory cells is organized into two first matrix sub-assemblies disposed symmetrically with respect to the reading circuit, all rows of the two first matrix sub-assemblies being parallel; and
the reading circuit is configured to carry out the differential readings of the pairs of effective threshold voltages of the depletion-type state transistors of pairs of symmetric memory cells located respectively in the two first matrix sub-assemblies on homologous columns of the two first matrix sub-assemblies.
4. The system according to claim 3, wherein the processing circuit includes a second assembly of non-volatile memory cells each having a second selection transistor embedded in the semiconductor substrate and a second depletion-type state transistor having a control gate and a floating gate, the memory cells of the second assembly configured to contain the reliability information, wherein the reliability information is representative of a reliability or unreliability of contents of the pairs of symmetric memory cells of the first assembly.
4. The system according to claim 3, wherein the processing circuit includes a second assembly of non-volatile memory cells each having a second selection transistor embedded in the semiconductor substrate and a second depletion-type state transistor having a control gate and a floating gate, the memory cells of the second assembly configured to contain reliability information representative of a reliability or unreliability of contents of the pairs of symmetric memory cells of the first assembly.
5. The system according to claim 4, wherein the second assembly includes a matrix arrangement of memory cells sharing same columns as those of the matrix arrangement of the memory cells of the first assembly.
5. The system according to claim 4, wherein the second assembly includes a matrix arrangement of memory cells sharing same columns as those of the matrix arrangement of the memory cells of the first assembly.
6. The system according to claim 5, wherein the second assembly includes two second matrix sub-assemblies distributed respectively on either side of the two first matrix sub-assemblies.
6. The system according to claim 5, wherein the second assembly includes two second matrix sub-assemblies distributed respectively on either side of the two first matrix sub-assemblies.
7. The system according to claim 5, wherein the reliability information associated with the pairs of symmetric memory cells is stored in memory cells of the second assembly located on the same column as those on which corresponding pairs of symmetric memory cells are located.
7. The system according to claim 5, wherein the reliability information associated with the pairs of symmetric memory cells is stored in memory cells of the second assembly located on the same column as those on which corresponding pairs of symmetric memory cells are located.
8. The system according to claim 4, wherein the processing circuit includes a first generating circuit configured to generate the reliability information in accordance with a margin value on the differential readings of the effective threshold voltages of the depletion-type state transistors of the pairs of symmetric memory cells.
8. The system according to claim 4, wherein the processing circuit includes a first generating circuit configured to generate the reliability information in accordance with a margin value on the differential readings of the effective threshold voltages of the depletion-type state transistors of the pairs of symmetric memory cells.
9. The system according to claim 8, wherein the first generating circuit comprises
the reading circuit configured to additionally carry out, for each pair of memory cells of the first assembly:
a first reading of a difference between a current flowing via a first memory cell of the pair increased by a reference current representative of the margin value, and a current flowing via a second memory cell of the pair, so as to obtain a first binary datum; and
a second reading of a difference between a current flowing via the second memory cell increased by the reference current, and the current flowing via the first memory cell, so as to obtain a second binary datum;
a comparison circuit configured to compare one of first or second binary data with an inverse of the other of the first and second binary data and to deliver the reliability information associated with the pair of memory cells, a logic value of which depends on a result of the comparison; and
a writing circuit for writing the reliability information in a corresponding memory cell of the second assembly.
9. The system according to claim 8, wherein the first generating circuit comprises
the reading circuit configured to additionally carry out, for each pair of memory cells of the first assembly:
a first reading of a difference between a current flowing via a first memory cell of the pair increased by a reference current representative of the margin value, and a current flowing via a second memory cell of the pair, so as to obtain a first binary datum; and
a second reading of a difference between a current flowing via the second memory cell increased by the reference current, and the current flowing via the first memory cell, so as to obtain a second binary datum;
a comparison circuit configured to compare one of first or second binary data with an inverse of the other of the first and second binary data and to deliver the reliability information associated with the pair of memory cells, a logic value of which depends on a result of the comparison; and
a writing circuit for writing the reliability information in a corresponding memory cell of the second assembly.
10. The system according to claim 8, wherein the first generating circuit comprises:
the reading circuit configured to carry out, for each pair of memory cells of the first assembly:
a first reading of a difference between a current flowing via a first memory cell of the pair increased by a reference current representative of the margin value, and a current flowing via a second memory cell of the pair, so as to obtain a first binary datum;
a second reading of a difference between the current flowing via the second memory cell increased by the reference current and, on the other hand, the current flowing via the first memory cell, so as to obtain a second binary datum;
a comparator configured to carry out:
a comparison of one of first or second binary data with an inverse of the other of the first and second binary data; and
a delivery of a piece of provisional reliability information associated with the pair of memory cells, a logic value of which depends on a result of the comparison; and
a writing circuit configured to:
write the piece of provisional reliability information in a corresponding memory cell of the second assembly; and
a control circuit configured to cause the reading circuit to perform an odd number of the first readings and the second readings and to cause the comparator to perform an odd number of the comparisons and the deliveries so as to obtain an odd number of pieces of provisional stored reliability information; and
a selection circuit configured to carry out a majority vote on the logic values of the provisional reliability information, so as to select the reliability information.
10. The system according to claim 8, wherein the first generating circuit comprises:
the reading circuit configured to carry out, for each pair of memory cells of the first assembly:
a) a first reading of a difference between a current flowing via a first memory cell of the pair increased by a reference current representative of the margin value, and a current flowing via a second memory cell of the pair, so as to obtain a first binary datum;
b) a second reading of a difference between the current flowing via the second memory cell increased by the reference current and, on the other hand, the current flowing via the first memory cell, so as to obtain a second binary datum;
a comparison circuit configured to:
c) compare one of first or second binary data with an inverse of the other of the first and second binary data; and
d) to deliver a piece of provisional reliability information associated with the pair of memory cells, a logic value of which depends on a result of the comparison; and
a writing circuit configured for:
e) writing the piece of provisional reliability information in a corresponding memory cell of the second assembly; and
a control circuit configured to execute, an odd number of times, by reading, comparing and writing, the steps a), b), c), d) and e) so as to obtain an odd number of pieces of provisional stored reliability information; and
a selection circuit configured to carry out a majority vote on the logic values of the provisional reliability information, so as to select the reliability information.
11. The system according to claim 4, wherein the processing circuit comprises a second generating circuit configured to generate the group of output data at least from the differential readings of the effective threshold voltages of the depletion-type state transistors of the pairs of symmetric memory cells, and the reliability information of the pairs of symmetric memory cells.
11. The system according to claim 4, wherein the processing circuit comprises a second generating circuit configured to generate the group of output data at least from the differential readings of the effective threshold voltages of the depletion-type state transistors of the pairs of symmetric memory cells, and the reliability information of the pairs of symmetric memory cells.
12. The system according to claim 11, wherein the second generating circuit is configured to generate the group of output data from differential readings of the effective threshold voltages of the depletion-type state transistors of the pairs of symmetric memory cells, addresses of the columns in which the pairs of symmetric memory cells are located and the reliability information of the pairs of symmetric memory cells.
12. The system according to claim 11, wherein the second generating circuit is configured to generate the group of output data from differential readings of the effective threshold voltages of the depletion-type state transistors of the pairs of symmetric memory cells, addresses of the columns in which the pairs of symmetric memory cells are located and the reliability information of the pairs of symmetric memory cells.
13. The system according to claim 12, wherein the second generating circuit comprises:
the reading circuit configured to carry out, for each pair of memory cells, the differential reading so as to obtain a first piece of binary information having a first logic value;
an inversion circuit configured to invert or not the first logic value as a function of the logic value of a low-weight bit of the address of the column in which the pair is located and to deliver a second piece of binary information having a second logic value; and
a masking circuit configured to retain the second piece of binary information as output data, only if the pair of memory cells is associated with a piece of reliability information designating it as reliable.
13. The system according to claim 12, wherein the second generating circuit comprises:
the reading circuit configured to carry out, for each pair of memory cells, the differential reading so as to obtain a first piece of binary information having a first logic value;
an inversion circuit configured to invert or not the first logic value as a function of the logic value of a low-weight bit of the address of the column in which the pair is located and to deliver a second piece of binary information having a second logic value; and
a masking circuit configured to retain the second piece of binary information as output data, only if the pair of memory cells is associated with a piece of reliability information designating it as reliable.
14. The system according to claim 4, wherein the first assembly of non-volatile memory cells, the second assembly of non-volatile memory cells and the processing circuit are located within a same integrated circuit.
14. The system according to claim 4, wherein the first assembly of non-volatile memory cells, the second assembly of non-volatile memory cells and the processing circuit are located within a same integrated circuit.
15. The system according to claim 14, wherein the system is a system-on-chip comprising:
the same integrated circuit;
a coding/decoding circuit configured to use the group of output data as encryption/decryption key;
a control circuit configured to deliver, to the same integrated circuit, control logic signals and analog voltage signals; and
another non-volatile memory.
15. The system according to claim 14, wherein the system is a system-on-chip comprising:
the same integrated circuit;
a coding/decoding circuit configured to use the group of output data as encryption/decryption key;
a control circuit configured to deliver, to the same integrated circuit, control logic signals and analog voltage signals; and
another non-volatile memory.
17. The method of claim 16, wherein:
the first assembly of non-volatile memory cells is organized into two first matrix sub-assemblies disposed symmetrically with respect to a reading circuit, all rows of the two first matrix sub-assemblies being parallel; and
the reading comprises differentially reading, by a reading circuit in the processing circuit, the effective threshold voltages of the state transistors of pairs of symmetric memory cells located respectively in the two first matrix sub-assemblies on homologous columns of the two first matrix sub-assemblies.
3. The system according to claim 1, wherein:
the processing circuit includes a reading circuit configured to carry out the differential readings;
the first assembly of non-volatile memory cells is organized into two first matrix sub-assemblies disposed symmetrically with respect to the reading circuit, all rows of the two first matrix sub-assemblies being parallel; and
the reading circuit is configured to carry out the differential readings of the pairs of effective threshold voltages of the depletion-type state transistors of pairs of symmetric memory cells located respectively in the two first matrix sub-assemblies on homologous columns of the two first matrix sub-assemblies.
19. The method according to claim 18, wherein each memory cell includes a gate oxide disposed between the floating gate of the depletion-type state transistor and the substrate, a thickness of the gate oxide being greater than 8 nanometers.
2. The system according to claim 1, wherein each memory cell includes a gate oxide disposed between the floating gate of the depletion-type state transistor and the substrate, a thickness of the gate oxide being greater than 8 nanometers.
20. The method according to claim 18, wherein:
the processing circuit includes a reading circuit configured to carry out the readings;
the first assembly of non-volatile memory cells is organized into two first matrix sub-assemblies disposed symmetrically with respect to the reading circuit, all rows of the two first matrix sub-assemblies being parallel; and
the reading circuit is configured to carry out differential readings of pairs of effective threshold voltages of the depletion-type state transistors of pairs of symmetric memory cells located respectively in the two first matrix sub-assemblies on homologous columns of the two first matrix sub-assemblies.
3. The system according to claim 1, wherein:
the processing circuit includes a reading circuit configured to carry out the differential readings;
the first assembly of non-volatile memory cells is organized into two first matrix sub-assemblies disposed symmetrically with respect to the reading circuit, all rows of the two first matrix sub-assemblies being parallel; and
the reading circuit is configured to carry out the differential readings of the pairs of effective threshold voltages of the depletion-type state transistors of pairs of symmetric memory cells located respectively in the two first matrix sub-assemblies on homologous columns of the two first matrix sub-assemblies.
Claim Objections
9. Independent claim 1 is objected to because of the following informalities:
A. Independent claim 1, on lines 5, 9 and at line 10, recites the following: “the state transistors …”There are two transistors recited prior to this limitation. It is not clear whether this limitation is referring to “a selection transistor’ or a “depletion-type transistor”. In order to avoid ambiguity and add clarity to the claim, the office suggests changing the above underlined claim limitation, “the state transistors” …” to “…the depletion-type state transistors”
Independent claim 1, on lines 8-9, recites the limitation, “the effective threshold voltages of the state transistors” and it should be corrected as “the respective effective threshold voltages of the depletion-type state transistors…” so that it is consistent to claim limitation recited on lines 5-6.
Furthermore, on line 9 and 10-11, independent claim 1 recites, “the memory cells of the first assembly”, it is not clear whether it is referring to the “a first assembly of non-volatile memory cells” recited on line 2.
In order to avoid this ambiguity, the office recommends changing, the above underlined claim limitation, “the memory cells of the first assembly”, to the “non-volatile memory cells of the first assembly”
Independent claim 1, on line 8 recites the following: “the output data…”
It is not clear whether this limitation is referring to “a group of output data” recited earlier. In order to avoid ambiguity and add clarity to the claim, the office suggests changing the limitation” the output data…” to “the group of output data…”
For the sake of examination, the claim is interpreted likewise as suggested above.
Appropriate correction is required.
B. Claim 15 on line 3 recites the limitation, “a coding/decoding circuit configured to use the group of output data as encryption/decryption key”. The limitation is confusing because it is unclear as whether it is the claimed coding circuit or the decoding circuit that uses the output data as an encryption key. Similarly, it is unclear as whether it is the claimed coding circuit or the decoding circuit that uses the output data as a decryption key.
Appropriate correction is required.
C. Independent claim 16 on line 2 and line 7, recites the following: “state transistor…”
It is not clear whether this limitation is the same as “a depletion type transistor” recited on line 5. In order to avoid ambiguity and add clarity to the claim, the office suggests changing the above underlined claim limitation, “state transistors” …” to “…depletion-type state transistors”
Appropriate correction is required.
Furthermore, independent claim 16, on line 3, recites the following: “the memory cells being arranged….” It is not clear whether this limitation is referring to the claim limitation, “a plurality of memory cells” recited on line 1. In order to avoid ambiguity, the office suggests changing the above underline claim limitation, “the memory cells being arrange…” to “the plurality of memory cells being arranged…”
Independent claim 16, on lines 7-8 recites the following: “the memory cells of the firs assembly” , it is not clear whether this limitation is referring to the claim limitation, “a first assembly on non-volatile memory cells” recited on line 3-4. In order to add clarity, the office suggest changing the above underlined claim limitation, “the memory cells of the firs assembly” to “the non-volatile memory cells of the first assembly”
For the sake of examination, the claim is interpreted likewise as suggested above.
D. Independent claim 18, on line 7 and at lines 11- 12, recites the following: “the state transistors …”There are two transistors recited prior to this limitation. It is not clear whether this limitation is referring to “a selection transistor’ or a “depletion-type transistor”. In order to avoid ambiguity and add clarity to the claim, the office suggests changing the above underlined claim limitation, “the state transistors” …” to “…the depletion-type state transistors”
Independent claim 18, on lines 10-11, recites the limitation, “the effective threshold voltages of the state transistors” and it should be corrected as “the respective effective threshold voltages of the depletion-type state transistors…” so that it is consistent to claim limitation recited on lines 7-8.
Furthermore, independent claim 18, on line 11 and 12-13, recites, “the memory cells of the first assembly”, it is not clear whether this is referring to the “a first assembly of non-volatile memory cells” recited on line 5.
In order to avoid this ambiguity, the office recommends changing, the above underlined claim limitations, “the memory cells of the first assembly”, to the “non-volatile memory cells of the first assembly”
Independent claim 18, on line 10 recites the following: “the output data…”
It is not clear whether this limitation is referring to “a group of output data” recited earlier. In order to avoid ambiguity and add clarity to the claim, the office suggests changing the limitation” the output data…” to “the group of output data…”
Appropriate correction is required.
For the sake of examination, the claim is interpreted likewise as suggested above.
E. Independent claim 18 is objected to since it is a method claim without any additional details on the recited manufacturing step.
The claim only recites a step of manufacturing. The rest of the limitations are about what the various components the claimed PUF device is made of as well as the steps performed by the various components, without additional details on the recited manufacturing step.
The recited method claim 18 should be further modified to better reflect the claimed manufacturing step by including the additional language. For example, the claim can be modified to recite:
… manufacturing an integrated circuit comprising a physical unclonable function device, said manufacturing of the physical unclonable function device including:
providing a first assembly of non-volatile memory cells each having a selection transistor embedded in a semiconductor substrate and a depletion-type state transistor having a control gate and a floating gate that are electrically connected, the state transistors having respective effective threshold voltages belonging to a common random distribution; and
providing a processing circuit configured to deliver, to an output interface of the device, a group of output data, wherein the output data is based on a reading of the effective threshold voltages of the state transistors of the memory cells of the first assembly, and is based on a corresponding group of reliability data corresponding with the state transistors of the memory cells of the first assembly.
Appropriate correction is required.
For the sake of examination, the claim is interpreted likewise as suggested above.
Claim Rejections - 35 USC § 103
10. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
11. Claims 1-3, 16-17 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over La Rosa et al (La Rosa), (US Publication No. 2013/0228846 A1, Pub. Date: Sep. 5, 2013) in view of Larry Wang (Wang), (US Publication No. 2019/0068383 A1, Pub. Date: Feb. 28, 2019) and in further view of Mai et al (Mai), (US Publication No. 2017/0180140 A1)
The following is referring to independent claims 1, 16 and 18:
As per independent claim 1, La Rosa discloses a method comprising:
generating, by a digital a system comprising: a [Para. 0013, “is an integrated circuit comprising at least two memory cells formed in a semiconductor substrate” The integrated circuit meets the limitation “the device”. Examiner Note: a physical unclonable function device is a type of Integrated circuit (IC)], comprising:
a first assembly of non-volatile memory cells each having a selection transistor embedded in a semiconductor substrate [Para. 0013 see figure 4 and 9, is an integrated circuit comprising at least two memory cells formed in a semiconductor substrate, each comprising a selection transistor. Para. 0002, The present disclosure relates to nonvolatile memories in integrated circuits on semiconductor chip. Figure 4 and Figure 1, which is an integrated circuit comprising two non-volatile memory cells that contains both selection transistor ST11 and ST12, meets the limitation “a first assembly”] and a depletion-type state transistor having a control gate and a floating gate that are electrically connected [See figure 4 and Para. 0004, Each memory cell C11, C12 comprises a floating gate transistor FGT11, FGT12 that meets the limitation of “depletion-type state transistor” and a selection transistor ST11, ST12. Each floating gate transistor comprises …a floating gate FG, and a control gate CG, and see figure 4, shows how the floating gate FG and the control gate CG are electronically connected. Examiner Note: The office interprets the floating gate transistor FGT31/FGT32 as depletion-type since a. FGT31/FGT32 at erased state Conducts at zero/low gate voltages. B. FGT31/FGT32, floating-gate charge shift where threshold can be negative. C. FGT31/FGT32 during read mode channel is active without strong gate bias and d. FGT31/FGT32 floating-gate charge distribution is conductance controlled by charge not gate. See at least para. 0011, the steps of programming, erasure, and read are performed with low value voltages by exploiting the potential difference between the substrate and the control gate of floating gate transistors. At the end of this office action, the office cites another prior arts to support examiner’s interpretation and how “the floating gate transistor” could become and interpreted as a “depletion-type state transistor” as defined in La Rose’s prior art, For instance US Patent No. 5293328 A to Amin discloses the following that supports the office’s interpretation: “FEEPROM memory cell transistor is considered programmed when it is in the high threshold voltage state, i.e. when its floating gate is negatively charged with trapped injected electrons. FEEPROM memory cell is typically assumed to store a logic "0" when in the programmed state. Similar to UV-EPROM, FEEPROM is programmed by injecting hot electrons into the floating gate of the memory cell. A FEEPROM memory cell is considered erased when it is in the low threshold voltage state, i.e. when its floating gate is depleted from trapped injected electrons. (See also other cited prior arts US Patent No. 4612630 shown at the end of this office action for supporting this interpretation)]
the state transistors having respective effective threshold voltages [Para. 0060, threshold voltage of the transistor FGT12 in order to ensure that the transistor FGT12 remains in the blocked state. The threshold voltage is a function of the state of the transistor, Para. 0008, Thus, during a read of cell C11, the selection transistor ST12 receives the blocking voltage Voff and is not conducting. A current (represented by an arrow in FIG. 3) flows through the channel region CH1 of the transistor FGT11 and through the channel region CH2 of the transistor ST11. This current is representative of the threshold voltage of the transistor FGT11. The threshold voltage is representative of a programmed or erased state of the transistor, which depends on a quantity of electrical charges stored in its floating gate] and a processing circuit [See the circuit shown at least on figure 9 that is used for reading memory cells, “para.0031, FIG. 9 shows a method according to the disclosure of reading a memory cell of the pair of memory cells of FIG. 6”]configured to read a data, [0031 and figure 9, IG. 9 shows a method according to the disclosure of reading a memory cell of the pair of memory cells of FIG. 6 and Para. 0060-0061, The threshold voltage is a function of the state of the transistor, programmed... In other words, the selection transistor ST12, usually used for the selection for read of a memory cell, .., and the floating gate transistor FGT12 is forced into the blocked state. Thus, a feature of this read method is that the voltages applied to the gates of the selection transistors ST11, ST12 are identical no matter which memory cell is read in the pair of memory cells. And para. 0072, FIG. 5, table RD3 in Annex 1 describes voltage values applied to the memory cells during the read of the memory cell C21. Para. 0008, during a read of cell C11, the selection transistor ST12 receives the blocking voltage Voff. A current (represented by an arrow in FIG. 3) flows through the channel region CH1 of the transistor FGT11 and through the channel region CH2 of the transistor ST11. This current is representative of the threshold voltage of the transistor FGT11. The threshold voltage is representative of a programmed or erased state of the transistor, which depends on a quantity of electrical charges stored in its floating gate. This current is sensed by a sense amplifier, not shown in the figure, which supplies a binary data stored by the cell C11. Para.0115, sense amplifiers SA, which apply, during the read of memory cells, the appropriate voltages BLV to the different bitlines BL, and supply a binary word read in the memory, for example a word of 8 bits B0-B7. Note: The binary data that is read and supplied from the memory which is based the effective threshold voltages of the state transistors of the memory cells meets the limitation, “a processing circuit configured to read a data, the data that is based on readings of the effective threshold voltages of the state transistors of the memory cells” Furthermore Para. 0080, FIG. 9, table RD4 in Annex 1 describes voltage values applied to the memory cells during the read of the memory cell C31 and Para. 0081, In FIG. 9, arrows show a current traversing the channel region CH1 of the transistor FGT31 and the vertical channel region CH2 of the transistor ST31] of the first assembly [Figure 9, 4 and Figure 1, which is an integrated circuit comprising two non-volatile memory cells that contains both selection transistor ST11 and ST12, meets the limitation “a first assembly”] ,
La Rose doesn’t explicitly disclose the following underlined claim limitation:
“…physical unclonable function comprising
“…the state transistors having respective effective threshold voltages belonging to a common random distribution
a processing circuit configured to deliver, to an output interface of the device, a group of output data, wherein the output the data that is based on readings of the effective threshold voltages of the state transistors of the memory cells
However, Wang explicitly discloses the above underlined claim limitation:
“physical unclonable function comprising a first assembly of non-volatile memory cells each having a selection transistor embedded in a semiconductor substrate” [Para. 0004, he input signals form a PUF (Physical Unclonable Function) challenge signal to the integrated circuit and the output signals form a PUF (Physical Unclonable Function) response signal to the challenge signal. Para. 0004-0005, the present invention provides for an integrated circuit which has an array OTP (One-Time Programmable) memory cells/non-volatile memory cells. Each OTP memory cell is programmable by rupturing a gate oxide layer in the OTP memory cell. Para. 0014, he memory cell has a pass MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a programmable element in the form of a second (MOSFET) transistor. The pass or select transistor is formed by a gate electrode 17 slightly removed from and spanning two N+ source/ drain regions 13 and 14 located in a semiconductor body 12 of P-conductivity. ]
the state transistors having respective effective threshold voltages belonging to a common random distribution [Para. 0002, the random variability of some semiconductor device parameters has been used or considered for security applications. These parameters include the threshold voltage VT of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), the on-current, and metal resistance. Para. 0030, The PUF integrated circuit can be used for authentication and the key generation for cryptographic ciphers, for example. The programmed OTP memory cell as described relies upon a semiconductor parameter which is a random, but stable, physical effect. The programmed OTP memory cell array is unique, stable, has low implementation cost and low risk of modeling.….Para. 0013, the present invention uses the breakdown of the gate oxide in OTP memory cells for the generation of PUF signals. The oxide breakdown is highly variable over the cells in the array due to the random nature of the thickness of the oxide and of the shape and quality of the oxide. A problem with the OTP memory cell is the variability in the quality of the programmed connection. Gate oxide breakdown can vary. With a particular read voltage on the gate of a selected programmed memory cell, the bit line current varies according to the quality…the gate oxide of the programming element of the memory cell. Note: The random variability in oxide thickness causes random, unpredictable variations in threshold behavior. That corresponds to effective threshold voltages belonging to a random distribution”]
a processing circuit configured to deliver, to an output interface of the device, a group of output data[See figure 5, where the OTP memory cell array is used as interface device for a challenge and to deliver an output response data which is a PUF data/a group of data/ a group of PUF response bits such as 128 bits. Para. 0030, FIG. 5 shows how the PUF integrated circuit might operate at a general level. The integrated circuit as part of a device or system receives a PUF challenge signal and sends back a PUF response signal comprising the contents of the programmed OTP memory array. The PUF integrated circuit can be used for authentication and the key generation for cryptographic ciphers, for example. The programmed OTP memory cell as described relies upon a semiconductor parameter which is a random. See also claims 20-22, transmitting the contents of the OTP memory cell array; whereby the transmitted contents correspond to a PUF response signal to the PUF challenge signal… wherein the transmitted contents of the programmed OTP memory cell array comprise at least 128 bit and wherein the n bits of the PUF response signal comprises at least 128 bits] wherein the output data that is based on readings of the effective threshold voltages of the state transistors of the memory cells [Para. 0021, With a particular read voltage on the gate of a selected programmed memory cell cell, the bit line current varies according to the quality of the conducting plug formed by the rupture of the gate oxide of the programming element of the memory cell….The present invention utilizes this variability in the gate of oxide breakdown for a PUF (Physically Unclonable Function) integrated circuit. And claim 7, In integrated circuit having an array of OTP memory cells, each OTP memory cell having a gate oxide for programming the memory cell, the array having approximately half of the memory cells programmed cell by the steps of: initially programming the array of OTP memory cells with a first voltage, the first voltage predetermined to program approximately half of the memory cells;….wherein the pattern of programmed and unprogrammed OTP memory cells responsive to gate oxide variations in the OTP memory cells forms a PUF signal/group of output data. Para. 0002, he random variability of some semiconductor device parameters has been used or considered for security applications. These parameters include the threshold voltage V.sub.T of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), the on-current, and metal resistance. ]
La Rosa and Wang are analogous in the same field of endeavor as they both are directed to an integrated circuit comprising memory cells.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to implement in the system of La Rosa a random mechanism such as “…physical unclonable function comprisingbelonging to a common random distribution and a processing circuit configured to deliver, to an output interface of the device, a group of output data” as per teaching of Wang for providing secure physical unclonable function for generating a secure PUF value/signal from OTP memory cell array using a large variations in the conductivity of the programmed memory cells.[ Wang, Para. 0029, Creating secure PUF signal and see abstract, The resulting large variations in the conductivity of the programmed memory cells in an OTP memory cell array is used for a PUF (Physically Unclonable Function). A method of obtaining a PUF value from an OTP memory cell array]
The combination of La Rose and Wang doesn’t explicitly disclose the following underlined claim limitation: “wherein the output the data based on that is based on corresponding reliability information corresponding with the state transistors of the memory cells of the first assembly
However, Mai explicitly discloses: wherein the output the data that is based on corresponding reliability information corresponding with the state transistors of the memory cells of the first assembly[See abstract, obtaining, by a response generator circuit, reliability information for each bit of an array of bits provided by a physical unclonable function (PUF) circuit; receiving, from the PUF circuit during run time, an array of values for the array of bits; selecting a plurality of values from the array of values received from the PUF circuit in accordance with the reliability information; and generating, by the response generator circuit, a PUF response from the selected plurality of values. Para, 0022, fIG. 2 is a schematic of an example of a sense amplifier (SA) 200 that can be used in the PUF array 106. The SA 200 is a latch-style SA with a bi-stable portion in the center. SAs are clocked circuits that amplify small differential voltages into full swing digital values and are can be used in memory read paths and as voltage comparators…. Random variations are a result of random uncertainties in the fabrication process such as random dopant fluctuation (fluctuations in the number and location of dopants in the transistor channel) and gate line-edge roughness].
La Rosa, Wang and Mai are all analogous in the same field of endeavor as they all are directed to an integrated circuit comprising memory cells.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to implement in the system of La Rosa and Wang to add a reliability information such as “wherein the output the data that is based on corresponding reliability information corresponding with the state transistors of the memory cells of the first assembly” as per teaching of Mai for enhancing the security of the system by generating a more reliable PUFs, for applications such as key generation that may require the PUF response to be perfectly reliable. [See Mai, para. 0006, without significant loss of security, all applications can benefit from more reliable PUFs, and applications such as key generation may require the PUF response to be perfectly reliable]
As per independent claim 16, La Rosa discloses a method of operating a system [[Para. 0013 discloses a method of operating an integrated circuit, “is an integrated circuit comprising at least two memory cells formed in a semiconductor substrate” The integrated circuit meets the limitation “the device”. Examiner Note: a physical unclonable function device is a type of Integrated circuit (IC)], the method comprising:
reading effective threshold voltages of state transistors of a plurality of memory cells [[Para. 0021, With a particular read voltage on the gate of a selected programmed memory cell cell, the bit line current varies according to the quality of the conducting plug formed by the rupture of the gate oxide of the programming element of the memory cell….The present invention utilizes this variability in the gate of oxide breakdown for a PUF (Physically Unclonable Function) integrated circuit. And claim 7, In integrated circuit having an array of OTP memory cells, each OTP memory cell having a gate oxide for programming the memory cell, the array having approximately half of the memory cells programmed cell by the steps of: initially programming the array of OTP memory cells with a first voltage, the first voltage predetermined to program approximately half of the memory cells;….wherein the pattern of programmed and unprogrammed OTP memory cells responsive to gate oxide variations in the OTP memory cells forms a PUF signal/group of output data. Para. 0002, he random variability of some semiconductor device parameters has been used or considered for security applications. These parameters include the threshold voltage V.sub.T of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), the on-current, and metal resistance. ] of a physical unclonable function device[[Para. 0013, “is an integrated circuit comprising at least two memory cells formed in a semiconductor substrate” The integrated circuit meets the limitation “the device”. Examiner Note: a physical unclonable function device is a type of Integrated circuit (IC)], the memory cells being arranged in a first assembly of non-volatile memory cells each having a selection transistor embedded in a semiconductor substrate [Para. 0013 see figure 4 and 9, is an integrated circuit comprising at least two memory cells formed in a semiconductor substrate, each comprising a selection transistor. Para. 0002, The present disclosure relates to nonvolatile memories in integrated circuits on semiconductor chip. Figure 4 and Figure 1, which is an integrated circuit comprising two non-volatile memory cells that contains both selection transistor ST11 and ST12, meets the limitation “a first assembly”] and a depletion type state transistor having a control gate and a floating gate that are electrically connected [connected [See figure 4 and Para. 0004, Each memory cell C11, C12 comprises a floating gate transistor FGT11, FGT12 that meets the limitation of “depletion-type state transistor” and a selection transistor ST11, ST12. Each floating gate transistor comprises …a floating gate FG, and a control gate CG, and see figure 4, shows how the floating gate FG and the control gate CG are electronically connected. Examiner Note: The office interprets the floating gate transistor FGT31/FGT32 as depletion-type since a. FGT31/FGT32 at erased state Conducts at zero/low gate voltages. B. FGT31/FGT32, floating-gate charge shift where threshold can be negative. C. FGT31/FGT32 during read mode channel is active without strong gate bias and FGT31/FGT32 floating-gate charge distribution is conductance controlled by charge not gate. See at least para. 0011, the steps of programming, erasure, and read are performed with low value voltages by exploiting the potential difference between the substrate and the control gate of floating gate transistors. At the end of this office action, the office cites another prior arts to support examiner’s interpretation and how “the floating gate transistor” could become and interpreted as a “depletion-type state transistor”, For instance US Patent No. 5293328 A to Amin discloses the following that supports the office’s interpretation: “FEEPROM memory cell transistor is considered programmed when it is in the high threshold voltage state, i.e. when its floating gate is negatively charged with trapped injected electrons. FEEPROM memory cell is typically assumed to store a logic "0" when in the programmed state. Similar to UV-EPROM, FEEPROM is programmed by injecting hot electrons into the floating gate of the memory cell. A FEEPROM memory cell is considered erased when it is in the low threshold voltage state, i.e. when its floating gate is depleted from trapped injected electrons. (See also other cited prior arts shown at the end of this office action)];
reading with a processing circuit [[See the circuit shown at least on figure 9 that is used for reading memory cells, “para.0031, FIG. 9 shows a method according to the disclosure of reading a memory cell of the pair of memory cells of FIG. 6”], [0031 and figure 9, IG. 9 shows a method according to the disclosure of reading a memory cell of the pair of memory cells of FIG. 6 and Para. 0060-0061, The threshold voltage is a function of the state of the transistor, programmed... In other words, the selection transistor ST12, usually used for the selection for read of a memory cell, .., and the floating gate transistor FGT12 is forced into the blocked state. Thus, a feature of this read method is that the voltages applied to the gates of the selection transistors ST11, ST12 are identical no matter which memory cell is read in the pair of memory cells. And para. 0072, FIG. 5, table RD3 in Annex 1 describes voltage values applied to the memory cells during the read of the memory cell C21. Para. 0008, during a read of cell C11, the selection transistor ST12 receives the blocking voltage Voff. A current (represented by an arrow in FIG. 3) flows through the channel region CH1 of the transistor FGT11 and through the channel region CH2 of the transistor ST11. This current is representative of the threshold voltage of the transistor FGT11. The threshold voltage is representative of a programmed or erased state of the transistor, which depends on a quantity of electrical charges stored in its floating gate. This current is sensed by a sense amplifier, not shown in the figure, which supplies a binary data stored by the cell C11. Para.0115, sense amplifiers SA, which apply, during the read of memory cells, the appropriate voltages BLV to the different bitlines BL, and supply a binary word read in the memory, for example a word of 8 bits B0-B7. Note: The binary data that is read and supplied from the memory which is based the effective threshold voltages of the state transistors of the memory cells meets the limitation, “a processing circuit configured to read a data, the data that is based on readings of the effective threshold voltages of the state transistors of the memory cells” Furthermore Para. 0080, FIG. 9, table RD4 in Annex 1 describes voltage values applied to the memory cells during the read of the memory cell C31 and Para. 0081, In FIG. 9, arrows show a current traversing the channel region CH1 of the transistor FGT31 and the vertical channel region CH2 of the transistor ST31] device [Figure 9, 4 and Figure 1, which is an integrated circuit comprising two non-volatile memory cells that contains both selection transistor ST11 and ST12, meets the limitation “a first assembly”] ,.
La Rose doesn’t explicitly disclose the following underlined claim limitation:
“…physical unclonable function comprising
Generating with the processing circuit output data based on readings of the effective threshold voltages … and delivering, the output data to an output interface of the physical unclonable function device
However, Wang explicitly discloses the above underlined claim limitation:
“physical unclonable function comprising a first assembly of non-volatile memory cells each having a selection transistor embedded in a semiconductor substrate” [Para. 0004, he input signals form a PUF (Physical Unclonable Function) challenge signal to the integrated circuit and the output signals form a PUF (Physical Unclonable Function) response signal to the challenge signal. Para. 0004-0005, the present invention provides for an integrated circuit which has an array OTP (One-Time Programmable) memory cells/non-volatile memory cells. Each OTP memory cell is programmable by rupturing a gate oxide layer in the OTP memory cell. Para. 0014, he memory cell has a pass MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a programmable element in the form of a second (MOSFET) transistor. The pass or select transistor is formed by a gate electrode 17 slightly removed from and spanning two N+ source/ drain regions 13 and 14 located in a semiconductor body 12 of P-conductivity. ]
Generating with the processing circuit output data based on readings of the effective threshold voltages … and delivering, the output data to an output interface of the physical unclonable function device [See figure 5, where the OTP memory cell array is used as interface device for a challenge and to deliver an output response data which is a PUF data/a group of data/ a group of PUF response bits such as 128 bits. Para. 0030, FIG. 5 shows how the PUF integrated circuit might operate at a general level. The integrated circuit as part of a device or system receives a PUF challenge signal and sends back a PUF response signal comprising the contents of the programmed OTP memory array. The PUF integrated circuit can be used for authentication and the key generation for cryptographic ciphers, for example. The programmed OTP memory cell as described relies upon a semiconductor parameter which is a random. See also claims 20-22, transmitting the contents of the OTP memory cell array; whereby the transmitted contents correspond to a PUF response signal to the PUF challenge signal… wherein the transmitted contents of the programmed OTP memory cell array comprise at least 128 bit and wherein the n bits of the PUF response signal comprises at least 128 bits] the data that is based on readings of the effective threshold voltages of the state transistors of the memory cells [Para. 0021, With a particular read voltage on the gate of a selected programmed memory cell cell, the bit line current varies according to the quality of the conducting plug formed by the rupture of the gate oxide of the programming element of the memory cell….The present invention utilizes this variability in the gate of oxide breakdown for a PUF (Physically Unclonable Function) integrated circuit. And claim 7, In integrated circuit having an array of OTP memory cells, each OTP memory cell having a gate oxide for programming the memory cell, the array having approximately half of the memory cells programmed cell by the steps of: initially programming the array of OTP memory cells with a first voltage, the first voltage predetermined to program approximately half of the memory cells;….wherein the pattern of programmed and unprogrammed OTP memory cells responsive to gate oxide variations in the OTP memory cells forms a PUF signal/group of output data. Para. 0002, he random variability of some semiconductor device parameters has been used or considered for security applications. These parameters include the threshold voltage V.sub.T of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), the on-current, and metal resistance. ]
La Rosa and Wang are analogous in the same field of endeavor as they both are directed to an integrated circuit comprising memory cells.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to implement in the system of La Rosa additional PUF mechanism such as “…physical unclonable function comprising a first assembly of non-volatile memory cells each having a selection transistor embedded in a semiconductor substrate” and “Generating with the processing circuit output data based on readings of the effective threshold voltages … and delivering, the output data to an output interface of the physical unclonable function device ” as per teaching of Wang for providing secure physical unclonable function for generating a secure PUF value/signal from OTP memory cell array using a large variations in the conductivity of the programmed memory cells.[ Wang, Para. 0029, Creating secure PUF signal and see abstract, The resulting large variations in the conductivity of the programmed memory cells in an OTP memory cell array is used for a PUF (Physically Unclonable Function). A method of obtaining a PUF value from an OTP memory cell array]
The combination of La Rose and Wang doesn’t explicitly disclose the following underlined claim limitation:
“accessing reliability information corresponding with the state transistors of the memory cells of the first assembly;
“output the data based on that is based on corresponding reliability information .
However, Mai explicitly discloses this underlined claim limitation : accessing reliability information corresponding with the state transistors of the memory cells of the first assembly; “output the data based on that is based on corresponding reliability information [See abstract, obtaining, by a response generator circuit, reliability information for each bit of an array of bits provided by a physical unclonable function (PUF) circuit; receiving, from the PUF circuit during run time, an array of values for the array of bits; selecting a plurality of values from the array of values received from the PUF circuit in accordance with the reliability information; and generating, by the response generator circuit, a PUF response from the selected plurality of values. Para, 0022, fIG. 2 is a schematic of an example of a sense amplifier (SA) 200 that can be used in the PUF array 106. The SA 200 is a latch-style SA with a bi-stable portion in the center. SAs are clocked circuits that amplify small differential voltages into full swing digital values and are can be used in memory read paths and as voltage comparators…. Random variations are a result of random uncertainties in the fabrication process such as random dopant fluctuation (fluctuations in the number and location of dopants in the transistor channel) and gate line-edge roughness].
La Rosa, Wang and Mai are all analogous in the same field of endeavor as they all are directed to an integrated circuit comprising memory cells.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to implement in the system of La Rosa and Wang to add a reliability information such as “accessing reliability information corresponding with the state transistors of the memory cells of the first assembly; “output the data based on that is based on corresponding reliability information ” as per teaching of Mai for enhancing the security of the system by generating a more reliable PUFs, for applications such as key generation that may require the PUF response to be perfectly reliable. [See Mai, para. 0006, without significant loss of security, all applications can benefit from more reliable PUFs, and applications such as key generation may require the PUF response to be perfectly reliable].
As per independent claim 18, independent claim 18, has the same scope as that of the above independent claim 1. It’s rejected for the same reasons as that of the above independent claim 1. The additional claim limitation which is new in claim 18 is “manufacturing an integrated circuit”. This limitation is disclosed by at least a primary prior art La Rosa. For instance, La Rosa on at least paragraph 0018 discloses “a method of manufacturing on a semiconductor substrate at least two memory cells, each comprising a selection transistor, comprising the steps of implanting a buried source line in the substrate, forming in the substrate a common buried gate of the selection transistors,”
The following is referring to dependent claims 2-3 and 17-20:
As per dependent claim 2, the combination of La Rosa, Wang and Mai discloses the method/system as applied to claim 1 above. Furthermore, La Rosa discloses the method/system, wherein each memory cell includes a gate oxide disposed between the floating gate of the depletion-type state transistor and the substrate [Figure 6 and figure 9, and para. 0073, This vertical gate SGC is buried in the substrate PW and is electrically isolated from adjacent structures by means of an isolating layer 12, for example of oxide SiO2, forming the gate oxide of the selection transistors ST31, ST32. It extends longitudinally vertically into the substrate PW from an upper surface of the substrate PW and has lower left and right edges that penetrate into the layer NISO. Para. 0092, a gate oxide layer 12 is deposited on the substrate PW and in the trenches 11. During a step S 14, FIG. 14D, a layer of polycrystalline silicon 13 is deposited on the substrate PW and in the trenches 11, above the oxide layer 12] a thickness of the gate oxide being greater than 8 nanometers.[ Para. 0180. a thickness comprised between 100 nanometers and 200 nanometers]
As per dependent claim 3, the combination of La Rosa, Wang and Mai discloses the method/system as applied to claim 1 above. Furthermore, La Rosa discloses the method/system, wherein: the processing circuit includes a
reading circuit configured to carry out the readings [[0031 and figure 9, IG. 9 shows a method according to the disclosure of reading a memory cell of the pair of memory cells of FIG. 6 and Para. 0060-0061, The threshold voltage is a function of the state of the transistor, programmed... In other words, the selection transistor ST12, usually used for the selection for read of a memory cell, .., and the floating gate transistor FGT12 is forced into the blocked state. Thus, a feature of this read method is that the voltages applied to the gates of the selection transistors ST11, ST12 are identical no matter which memory cell is read in the pair of memory cells. And para. 0072, FIG. 5, table RD3 in Annex 1 describes voltage values applied to the memory cells during the read of the memory cell C21. Para. 0008, during a read of cell C11, the selection transistor ST12 receives the blocking voltage Voff. A current (represented by an arrow in FIG. 3) flows through the channel region CH1 of the transistor FGT11 and through the channel region CH2 of the transistor ST11. This current is representative of the threshold voltage of the transistor FGT11. The threshold voltage is representative of a programmed or erased state of the transistor, which depends on a quantity of electrical charges stored in its floating gate. This current is sensed by a sense amplifier, not shown in the figure, which supplies a binary data stored by the cell C11. Para.0115, sense amplifiers SA, which apply, during the read of memory cells, the appropriate voltages BLV to the different bitlines BL, and supply a binary word read in the memory, for example a word of 8 bits B0-B7. Note: The binary data that is read and supplied from the memory which is based the effective threshold voltages of the state transistors of the memory cells meets the limitation, “a processing circuit configured to read a data, the data that is based on readings of the effective threshold voltages of the state transistors of the memory cells” Furthermore Para. 0080, FIG. 9, table RD4 in Annex 1 describes voltage values applied to the memory cells during the read of the memory cell C31 and Para. 0081, In FIG. 9, arrows show a current traversing the channel region CH1 of the transistor FGT31 and the vertical channel region CH2 of the transistor ST31]; the first assembly of non-volatile memory cells is organized into two first matrix sub-assemblies disposed symmetrically with respect to the reading circuit [Figure 6, 4 and 9, shows symmetrical placement of identical memory cell structures C21/C22 and C31/C32 and FGT31/FGT32 on opposite sides of the trench, forming two sub-assemblies. And para. 0061, where identical gate voltages are applied to pairs on both sides. “he voltages applied to the gates of the selection transistors ST11, ST12 are identical” These diagrams show two matrix-like structures arranged symmetrically], all rows of the two first matrix sub-assemblies being parallel [Figures 4, 6 and 9, shows two parallel haves of the trench-based memory array]; and the reading circuit is configured to carry out differential readings of pairs of effective threshold voltages of the depletion-type state transistors Para. 0021, With a particular read voltage on the gate of a selected programmed memory cell cell, the bit line current varies according to the quality of the conducting plug formed by the rupture of the gate oxide of the programming element of the memory cell….The present invention utilizes this variability in the gate of oxide breakdown for a PUF (Physically Unclonable Function) integrated circuit. And claim 7, In integrated circuit having an array of OTP memory cells, each OTP memory cell having a gate oxide for programming the memory cell, the array having approximately half of the memory cells programmed cell by the steps of: initially programming the array of OTP memory cells with a first voltage, the first voltage predetermined to program approximately half of the memory cells;….wherein the pattern of programmed and unprogrammed OTP memory cells responsive to gate oxide variations in the OTP memory cells forms a PUF signal/group of output data. Para. 0002, he random variability of some semiconductor device parameters has been used or considered for security applications. These parameters include the threshold voltage V.sub.T of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), the on-current, and metal resistance. ]of pairs of symmetric memory cells located respectively in the two first matrix sub-assemblies on homologous columns of the two first matrix sub-assemblies [Figure 4-12, repeatedly show paired of memory cells one on each side of the trench, sharing: the same bit line (offset symmetrically); the same word line and the same control gate and having identical geometries].
As per dependent claim 17, dependent claim 17, has the same scope as that of the above dependent claim 3. It’s rejected for the same reasons as that of the above dependent claim 3.
As per dependent claim 19, dependent claim 19, has the same scope as that of the above dependent claim 2. It’s rejected for the same reasons as that of the above dependent claim 2.
As per dependent claim 20, dependent claim 20, has the same scope as that of the above dependent claim 3. It’s rejected for the same reasons as that of the above dependent claim 3.
Allowable Subject Matter
12. Dependent claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Dependent claims 5-15 depend on the above dependent claims 4 and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
13. The following is an examiner’s statements of reasons for allowance:
Regarding dependent claim 4, the combination of La Rosa, Wang and Mai, including the rest of the cited prior arts and the prior art cited in the IDS, either taken alone or in combination neither anticipates nor renders obvious the claimed subject matter of the instant application that is taken as a whole including the following specific claim limitation recited in dependent claim 4 : “wherein the processing circuit includes a second assembly of non-volatile memory cells each having a second selection transistor embedded in the semiconductor substrate and a second depletion-type state transistor having a control gate and a floating gate, the memory cells of the second assembly configured to contain the reliability information, wherein the reliability information is representative of a reliability or unreliability of contents of the pairs of symmetric memory cells of the first assembly”
For this reason, the specific claim limitations recited in dependent claim 4 taken as whole are found to be allowable.
14. The dependent claims 5-15 which are dependent on the above dependent claim 4 being further limiting to the dependent claims, definite and enabled by the specification would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Examiner Note: dependent claim 15 is objected as shown on the beginning of the office action, and the objection should be overcome first to be allowable and should be rewritten in independent form including all of the limitations of the base claim and any intervening claims
Conclusion
15. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
A. US Patent No. 5293328 to Amin discloses A FEEPROM memory cell is considered erased when it is in the low threshold voltage state, i.e. when its floating gate is depleted from trapped injected electrons… An over-erased FEEPROM memory cell threshold voltage may result in a negative threshold voltage causing the over-erased FEEPROM cell to become a depletion transistor memory cell. [This supports the office interpretation of “depletion-type state”]
B. US Patent No. 4612630 to Rosier discloses, When an EEPROM cell is programmed, it is preferable that the cell behave as a depletion mode device, that is, having a VLT which is negative or less than zero volts. … The low threshold or programmed memory cell is programmed into depletion mode or having a threshold below zero. In order to determine those devices which are in the depletion mode, the control line 51 would have to be forced below zero volts and the switching point monitored which in this case would be from a low resistance to a high resistance value [This supports the office interpretation of “depletion-type state”]
C. US Patent No. 9966954B1 to Yang discloses Physically Unclonable Function (PUF) cells are described, suitable for CMOS technology, where each PUF cell is based upon a two-transistor amplifier design. A PUF cell includes a voltage generator followed by one or more amplifier stages. Also described is a method and apparatus for determining a dark bit mask for an array of PUF cells based on the two-transistor amplifier design.
D. See the other cited prior arts.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMSON B LEMMA whose telephone number is 571-272-3806. The examiner can normally be reached on M-F 8am-10pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shaw Yin Chen can be reached on to 571-272-8878. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SAMSON B LEMMA/Primary Examiner, Art Unit 2498