Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
1. Applicant's arguments filed December 9th, 2025 have been fully considered but they are not persuasive.
As Applicant’s arguments are directed toward limitations of the claims modified or added via amendment, they will be addressed in the rejections below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Abts (patent No. 11,360,934) in view of Clarke (patent application publication No. 2023/0057903).
Abts taught the invention substantially as claimed including (as to claim 1). A spatial architecture device comprising: a plurality of single instruction, multiple data (SIMD) processing elements (e.g., see col. 9, lines 25-28), the plurality of processing elements arranged in arrays of processing elements (tiles) (e.g., see figs. 1A,1B2A,2B,3); a plurality of array controllers(ICUs,320,325) (e.g.,, see col. 3, lines 46-52 an fig. 3)), each array controller connected to an array of processing elements(e.g., see fig. 3) and configured to control the array of processing elements to execute instructions in a SIMD fashion(e.g., see col. 9, lines 25-55 ); a plurality of instruction queues (e.g., see fig. 4,5), each instruction queue connected to an array controller of the plurality of array controllers (e.g., see figs. 3,4,5 and col. 5, lines 10-15) from the array controller(e.g., see col. 12, lines 53-col 13, line 4 and col. 10, lines 21-26), the array controller dequeues the sequence of instructions (10:21-39, instruction dispatch). Abts did not expressly detail a main controller configured to provide sequences of instructions to the plurality of instruction queues and the enqueuing to the array controller.
Clarke however taught array controller 106 loads an application into a partition of the DP array (e.g., see paragraph 0213 and fig. 1,16A,16B,18) loading tasks to task queues (e.g., see paragraph 0208) and issuing tasks to the array (e.g., see paragraph 0221-0222) also array controller 106 is capable of providing tasks to task queues of various DMA circuit (434,502,602) to move data into and out from DP array 102 (e.g., see paragraph 0190 and fig. ,4,5,6)[ also note as the Clarke reference is understood the DMA circuit along with the MM switch and stream switch and control registers together provide the operation of controller(e.g. see paragraphs 0076 and 0080 and 0088 for a respective tile, the control of task queue is performed and tasks are input to the dma and stored in the task queue(s) dma controls to dispatching task to the processor (e.g., see fig. 4).[This also provides queuing and enqueing tasks, which operate as instructions, to the controller for DMA/MM switch/stream switch which operate as a controller for a respective tile]
It would have been obvious to one of ordinary skill in the art to combine the teachings of Abts and Clarke. Both references were directed toward the problems of performing processing using an array in a data processor. One of ordinary skill in the art would have been motivated to incorporate the Clarke teaching of a main controller at least to facilitate transfer of application/tasks/instructions to the array to control the synchronized operation of the array so the array would process data via one or more applications in a properly timed/synchronized manner and reduce time for starting initialization of succeeding tasks which would improve throughput.
As to claim 2 Abts and Clarke taught The device of claim 1, Clarke taught wherein the main controller (array controller 106) is configured to process one thread to provide the sequences of instructions(e.g., see paragraphs 0196 and 0213 and 0215).
As to claim 3 Abts and Clarke taught The device of claim 1, Clarke taught wherein the main controller is configured to process a plurality of threads to provide the sequences of instructions (e.g., see paragraphs 0205 and 0206).
As to claim 4 Abts and Clarke taught The device of claim 3,Clairke taught wherein the main controller is configured to provide a sequence of instructions from one thread to one instruction queue (e.g., see paragraphs 0190 and 0193).
As to claim 5 Abts and Clarke taught The device of claim 3, Clarke taught wherein the main controller is configured to provide a sequence of instructions from one thread to multiple instruction queues (e.g., see fig. 16H and paragraph 0190 and 0193 and 0207)[note in the implementation where the array controller to partition ratio not being 1 to 1 includes in a least one embodiment, the controller controlling multiple partitions and therefore sending a tasks (i.e., a sequence of instruction) to multiple partitions and therefore to multiple respective task queues.
As to claim 6 Abts and Clarke taught The device of claim 1, Clarke taught wherein the main controller is a first main controller(106-1), the device further comprising a second main controller (106-2), wherein: the first main controller(106-1) is configured to provide first sequences of instructions to a first subset of the plurality of instruction queues; and the second main controller(106-2) is configured to provide second sequences of instructions to a second subset of the plurality of instruction queues(e.g., see fig. 16F)(e.g., see paragraphs 0193-0197 and 0202-0203) (e.g., see paragraph 0190 and fig. ,4,5,6)[note providing tasks to task queue corresponds to providing sequences of instruction to instruction queues].
As to claim 7 Abts and Clarke taught The device of claim 6, Clarke taught wherein: the first main controller(106-1) is configured to process a first plurality of threads to provide the first sequences of instructions to the first subset of the plurality of instruction queues; and the second main controller (106-2) is configured to process a second plurality of threads to provide the second sequences of instructions to the second subset of the plurality of instruction queues (e.g., see paragraphs 0198 and0202). As to each of the main controllers configured to process plural threads Clarke taught two controllers(e.g., see fig. 16C and more than two overlays (e.g., see fig. 2 and more than two rows of tiles in fig. 3,7). Therefore, one of ordinary skill would have been motivated to have implement each main controller to implement a to process plural threads to enable each main controller control to the multiple regions of the array to process multiple instances of the same type of process or different processes operations in parallel so the combined system could efficiently perform processing on large amounts of data. Increasing throughput.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Brewer (US 2019/0171604) discloses a processor with control and thread selection logic used to dispatch instructions to a configurable array.
Silberman (US 2019/0163483) discloses a processor with a dispatch unit and issue queue for enqueueing and dequeueing groups of instructions.
Brownscheidle (US 2016/0202992) discloses a processor with an instruction buffer and issue queue to handle dispatch of instruction groups.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183
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