DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claim 19 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II (method), there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/25/2026.
Applicant’s election of Invention I in the reply filed on 02/25/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 – 5, 8, 13, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Inagaki (US 2015/0357316 A1) in view of Hwang (US 2022/0071016 A1).
Regarding Claim 1, Inagaki (US 2015/0357316 A1) discloses a printed wiring board (Fig 1-11), comprising: a mounting conductor layer (layer with 160Fa) comprising a plurality of first electrodes (76FP) and a plurality of second electrodes (76SP); a connection conductor layer (layer with 158Fa) comprising a plurality of connection wirings (158Fa) such that the connection wirings electrically connect ([0028]) the first electrodes (76FP) and the second electrodes (76SP); a resin insulating layer (150Fb; [0054]) formed between the mounting conductor layer (layer with 160Fa) and the connection conductor layer (layer with 158Fa) and having a plurality of openings (openings in 150Fb for 160Fa); and a plurality of connection via conductors (160Fa) formed in the plurality of openings of the resin insulating layer and comprising a plurality of first connection via conductors (160Faf) and a plurality of second connection via conductors (160Fas) such that the first connection via conductors (160Faf) electrically connect ([0028]) the first electrodes (76FP) and the connection wirings (158Fa) and that the second connection via conductors (160Fas) electrically connect ([0028]) the second electrodes (76SP) and the connection wirings (at 158Fa).
Inagaki does not disclose wherein the resin insulating layer includes inorganic particles and resin such that the inorganic particles include first inorganic particles forming inner wall surfaces in the openings and second inorganic particles embedded in the resin insulating layer and that shapes of the first inorganic particles are different from shapes of the second inorganic particles.
Hwang (US 2022/0071016 A1) teaches of a printed wiring board (Fig 13-16) wherein a resin insulating layer (310) includes inorganic particles (312; [0071]) and resin (311) such that the inorganic particles include first inorganic particles (312 shown as a partial sphere or circle at the edge or surface of VH1,VH2) forming inner wall surfaces in the openings and second inorganic particles (312 shown as whole spheres or circles away from VH1) embedded in the resin insulating layer (311) and that shapes of the first inorganic particles are different from shapes of the second inorganic particles (see Fig 13-16).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as disclosed by Inagaki, wherein the resin insulating layer includes inorganic particles and resin such that the inorganic particles include first inorganic particles forming inner wall surfaces in the openings and second inorganic particles embedded in the resin insulating layer and that shapes of the first inorganic particles are different from shapes of the second inorganic particles as taught by Hwang, in order to provide a desired roughened surface, improve peel strength and improve product reliability (Hwang, [0036,0144]).
Regarding Claim 2, Inagaki in view of Hwang teaches the limitations of the preceding claim and Hwang further teaches the printed wiring board (Fig 13-16) according to claim 1, wherein the resin insulating layer (311) is formed such that the inner wall surfaces (at VH1) in the openings (VH) include the first inorganic particles ([312]) and the resin (311) and that the first inorganic particles (312) have flat parts (parts or portions as seen in Fig 14) forming the inner wall surfaces.
Regarding Claim 3, Inagaki in view of Hwang teaches the limitations of the preceding claim and Hwang further teaches the printed wiring board (Fig 13-16) according to claim 2, wherein each of the inner wall surfaces (Vh1,Vh2) has a substantially common surface (a surface formed of Vh1 and Vh2; [0140-0144]) comprising the flat parts (flat regions as seen in Fig 14; note that the claim as not structurally limited this claimed “parts”) and a surface (surface of 311 at VH) of the resin (311).
Regarding Claim 4, Inagaki in view of Hwang teaches the limitations of the preceding claim and Hwang further teaches the printed wiring board (Fig 13-16) according to claim 2, wherein each of the second inorganic particles (312 away from VH) has a spherical shape (312 shown as a whole sphere or circle away from VH1; see Fig 13-16 and [0023] defining a diameter), and each of the first inorganic particles (312 at VH) has a shape (see Fig 13-16) (formed by cutting the second inorganic particles (312) along a flat surface in a respective one of the openings (VH)).
Claim states “”however this does not represent product structure but rather refers to the process by which it is made; thus this is treated as a product-by-process. See MPEP 2113.
Regarding Claim 5, Inagaki in view of Hwang teaches the limitations of the preceding claim and Inagaki further discloses the printed wiring board (Fig 1-11) according to claim 1, wherein the resin insulating layer (150Fb; [0054]) is formed in contact with the connection conductor layer (layer with 158Fa).
Regarding Claims 8 and 14, Inagaki in view of Hwang teaches the limitations of the preceding claim and Inagaki further discloses the printed wiring board (Fig 1-11) according to claims 1 and 2, wherein the plurality of connection via conductors (160Fa) is formed such that the first connection via conductors (160Fa at 76FP) extend to one-end portions (portions or regions or parts at one part of 158Fa) of the connection wirings (158Fa), respectively, and that the second connection via conductors (160Fa at 76SP) extend to other-end portions (portions or regions or parts at other part of 158Fa) of the connection wirings, respectively.
Regarding Claim 13, Inagaki in view of Hwang teaches the limitations of the preceding claim and Inagaki further discloses the printed wiring board (Fig 1-11) according to claim 1 further comprising: a plurality of first bumps (72,76FL on 76FP; [0048,0081]) formed on the plurality of first electrodes (76FP) respectively and comprising one of solder (76FL) and plating (72; [0081]); and a plurality of second bumps (72,76FL on 76SP; [0048,0081]) formed on the plurality of second electrodes (76SP) respectively and comprising one of solder (76FL) and plating (72; [0081]).
Regarding Claim 20, Inagaki in view of Hwang teaches the limitations of the preceding claim and Hwang further teaches the printed wiring board (Fig 13-16) according to claim 1, wherein the forming the resin insulating layer (311) includes forming the openings (VH) such that the first inorganic particles (312) have protruding portions (not shown; [0141] “filler 312 exposed through the via hole VH are surface-treated using plasma”) protruding from the resin forming inner wall surfaces (VH1) in the openings, and removing ([0141-0144]) the protruding portions from the first inorganic particles (312) such that the first inorganic particles have exposed surfaces (VH2) forming the inner wall surfaces (VH1) in the openings (VH).
Claim(s) 6 – 7 are rejected under 35 U.S.C. 103 as being unpatentable over Inagaki (US 2015/0357316 A1) in view of Hwang (US 2022/0071016 A1) as applied to claim 1 above and further in view of Nagasawa (US 2009/0314526 A1).
Regarding Claim 6, Inagaki in view of Hwang teaches the limitations of the preceding claim.
Inagaki does not disclose the printed wiring board according to claim 1 further comprising: an adhesive layer formed between the connection conductor layer and the resin insulating layer such that the adhesive layer is in contact with the connection conductor layer and that the resin insulating layer is in contact with the adhesive layer.
Nagasawa (US 2009/0314526 A1) teaches of a printed wiring board (Fig 8) comprising: an adhesive layer (5; [0055]) formed between a connection conductor layer (6,7; [0054]) and a resin insulating layer (1; 9,16; [0032]) such that the adhesive layer (5) is in contact with the connection conductor layer (6,7) and that the resin insulating layer (1) is in contact with the adhesive layer (5).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as taught by Inagaki in view of Hwang, further comprising: an adhesive layer formed between the connection conductor layer and the resin insulating layer such that the adhesive layer is in contact with the connection conductor layer and that the resin insulating layer is in contact with the adhesive layer as taught by Nagasawa, in order to reduce thermal expansion, enhance adhesion strength, and improve reliability (Nagasawa, [0004,0008,0062]).
Regarding Claim 7, Inagaki in view of Hwang teaches the limitations of the preceding claim and Nagasawa further teaches the printed wiring board (Fig 8) according to claim 6, wherein the adhesive layer (5) includes a smooth film (see Fig 8 showing 5 having a smooth surface adjacent 7 as well as portions between 5 and 16) and has a protruding part (a portion of 5 about 10 at the interface between 5 and 16 is shown as a protruding portion of 5) protruding from the smooth film.
Claim(s) 9 – 12 and 15 – 18 are rejected under 35 U.S.C. 103 as being unpatentable over Inagaki (US 2015/0357316 A1) in view of Hwang (US 2022/0071016 A1) as applied to claims 1 and 2 above and further in view of Nishioka (US 2015/0163901 A1).
Regarding Claims 9 and 15, Inagaki in view of Hwang teaches the limitations of the preceding claim and Inagaki further discloses the printed wiring board (Fig 1-11) according to claims 1 and 2, wherein the connection conductor layer is formed such that the connection wirings (158Fa) are formed substantially parallel to each other (see Fig 11).
Inagaki does not disclose wherein, include a smallest connection wiring having a smallest width in a range of 1 μm to 3 μm and have spaces formed between adjacent connection wirings and including a smallest space having a smallest width in a range of 1 μm to 3 μm.
Nishioka (US 2015/0163901 A1) teaches of a printed wiring board (Fig 1), wherein a connection conductor layer is formed such that connection wirings (52,55,56,58) are formed substantially parallel to each other (see Fig 1(C)), include a smallest connection wiring having a smallest width in a range of 1 μm to 3 μm ([0022,0035,0040] e.g. 3 μm) and have spaces formed between adjacent connection wirings and including a smallest space having a smallest width in a range of 1 μm to 3 μm ([0022,0035,0040] e.g. 3 μm).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as taught by Inagaki in view of Hwang, wherein include a smallest connection wiring having a smallest width in a range of 1 μm to 3 μm and have spaces formed between adjacent connection wirings and including a smallest space having a smallest width in a range of 1 μm to 3 μm as taught by Nishioka, in order to prevent peeling and provide a fine pitch (Nishioka, [0034,0046]). Furthermore a finer pitch would allow for an increased density of wiring in the printed wiring board and thus allow for more electrical connections and capabilities in the board.
Regarding Claims 10 and 16, Inagaki in view of Hwang and Nishioka teaches the limitations of the preceding claim and Nishioka further teaches the printed wiring board (Fig 1) according to claims 9 and 15, wherein the connection conductor layer is formed such that the connection wirings (52,55,56,58) include a largest connection wiring having a largest width of 5 μm or less ([0022,0035,0040]; 3 to 10 μm e.g. 3 μm) and have a largest space having a largest width of 5 μm or less ([0022,0035,0040] 3 to 10 μm e.g. 3 μm).
Regarding Claims 11 and 17, Inagaki in view of Hwang and Nishioka teaches the limitations of the preceding claim and Nishioka further teaches the printed wiring board (Fig 1) according to claims 10 and 16, wherein the largest connection wiring (52,55,56,58) has a width of 3 μm or less ([0022,0035,0040] 3 to 10 μm e.g. 3 μm) and the largest space has a width of 3 μm or less ([0022,0035,0040] 3 to 10 μm e.g. 3 μm).
Regarding Claims 12 and 18, Inagaki in view of Hwang and Nishioka teaches the limitations of the preceding claim and Nishioka further teaches the printed wiring board (Fig 1) according to claims 9 and 15, wherein the connection conductor layer is formed such that each of the connection wirings has an aspect ratio in a range of 2.0 to 4.0 ([0022,0035,0040] width of 3 to 10 μm and thickness from 15 to 20 μm; e.g. thickness of 20 μm to width of 5 μm [Wingdings font/0xE0] aspect ratio of 4; note that the claim language nor specification defines “aspect ratio”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Nirengi (US 2024/0147617 A1) teaches of a wiring board comprising a seed layer formed with a plurality of layers (31a,31c,31d,32a,32d,32b) as well as an electrolytic plating layer (31,32c) formed on the plurality of seed layers. This could be used in a future 103 Rejection.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
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/ROSHN K VARGHESE/Primary Examiner, Art Unit 2896