DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Invention I in the reply filed on 04/23/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 5 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Urashima (US 2007/0045815 A1).
Regarding Claim 1, Urashima (US 2007/0045815 A1) discloses a substrate (Fig 1) with an embedded element (101,100,92), comprising: a core substrate (11) having one surface (12) and a cavity (90) recessed from the one surface (12) in a thickness direction; an element package (101,100,92) disposed in the cavity (90), the element package comprising one or more elements (101,100); and a substrate insulating material (33) surrounding at least part of the element package (101,100,92), wherein when observed from a side surface of the substrate (11) with the embedded element (101,100), the substrate (11) with the embedded element comprises a cavity area (an area about 90; note that this claimed area is not structurally defined nor limited) in which the cavity (90) is disposed and a substrate area (an area outside of 90; note that this claimed area is not structurally defined nor limited) outside of the cavity area, and wherein an absolute value of difference between an average thickness of the substrate area ([0073]; “the thickness of the substrate is preferably 0.2 mm or more to 1.0 mm or less”) and an average thickness of the cavity area ([0053] “the thickness of the ceramic capacitors 100, 101 is preferably between about 0.2 mm and 1.0 mm”; this is an area of the cavity area) is 50 μm or less (e.g. 0.2 mm – 0.2 mm = 0).
Regarding Claim 2, Urashima further discloses the substrate (Fig 1) with the embedded element of claim 1, wherein the element package (100,101,92) further comprises an element insulating material (92; [0055,0079]) surrounding the one or more elements (100,101), and wherein the element insulating material (92) comprises one selected from the group consisting of an epoxy-based resin ([0055] “epoxy resin”), a polyimide-based resin, a polyurethane-based resin, a polyester-based resin, an acrylate-based resin, a polyamide-based resin and a combination thereof.
Regarding Claim 4, Urashima further discloses the substrate (Fig 1) with the embedded element of claim 1, wherein a thickness of the core substrate (11) is 100 μm to 2,000 μm ([0073]; “the thickness of the substrate is preferably 0.2 mm or more to 1.0 mm or less”).
Regarding Claim 5, Urashima further discloses the substrate (Fig 1) with the embedded element of claim 1, wherein the core substrate further comprises a core via (16) penetrating the substrate area in the thickness direction.
Regarding Claim 9, Urashima further discloses the substrate (Fig 1) with the embedded element of claim 1, wherein a thickness of the element package is 335 μm to 665 μm ([0053] “the thickness of the ceramic capacitors 100, 101 is preferably between about 0.2 mm and 1.0 mm”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over Urashima (US 2007/0045815 A1) as applied to claim 1 above, and further in view of Darmawikarta (US 2024/0114622 A1).
Regarding Claim 3, Urashima discloses the limitations of the preceding claim.
Urashima does not disclose the substrate with the embedded element of claim 1, wherein the core substrate comprises a glass-based material, and wherein the glass-based material comprises one selected from the group consisting of borosilicate glass, soda-lime glass, lead glass, aluminosilicate glass, quartz glass and a combination thereof.
Darmawikarta (US 2024/0114622 A1) teaches of a substrate with the embedded element (Fig 1), wherein a core substrate (104) comprises a glass-based material ([0021] “core layer 104 may be a glass core layer. The glass core layer may include a silicate-based glass (e.g., lithium-silicate, borosilicate, aluminum silicate, etc.). In variations, the glass of the glass core layer is a lower quality glass (e.g., glass made with soda lime), or a higher quality glass (e.g., quartz glass made with fused silica)”), and wherein the glass-based material comprises one selected from the group consisting of borosilicate glass ([0021]), soda-lime glass ([0021]), lead glass, aluminosilicate glass ([0021]), quartz glass ([0021]) and a combination thereof.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate as disclosed by Urashima, wherein the core substrate comprises a glass-based material, and wherein the glass-based material comprises one selected from the group consisting of borosilicate glass, soda-lime glass, lead glass, aluminosilicate glass, quartz glass and a combination thereof as taught by Darmawikarta, in order to provide a higher quality substrate (Darmawikarta, [0021]). As the selection of a desired quality can also adjust manufacturing costs of the overall substrate.
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Urashima (US 2007/0045815 A1) as applied to claim 1 above, and further in view of Xu (US 2019/0371687 A1).
Regarding Claim 6, Urashima discloses the limitations of the preceding claim and Urashima further discloses the substrate (Fig 1) with the embedded element of claim 1, wherein the core substrate (11) comprises a core inner surface (inner wall of 90 as seen in Fig 5) surrounding the cavity (90).
Urashima does not disclose wherein the substrate with embedded the element further comprises a conductive layer disposed on the one surface and the core inner surface.
Xu (US 2019/0371687 A1) teaches of a substrate (Fig 1) with an embedded element (16), wherein a core substrate (12) comprises a core inner surface (24) surrounding a cavity (14), and wherein the substrate with embedded the element further comprises a conductive layer (30) disposed on the one surface and the core inner surface.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate as disclosed by Urashima, wherein the substrate with embedded the element further comprises a conductive layer disposed on the one surface and the core inner surface as taught by Xu, in order to allow electrical transmission of signals between an embedded component and substrate, reduce overall size of the cavity, reduce the overall size of the substrate, and reduce costs (Xu, [0001,0024,0035,0037]).
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Urashima (US 2007/0045815 A1) as applied to claim 1 above, and further in view of Mikado (US 2013/0194764 A1).
Regarding Claim 7, Urashima further discloses the substrate (Fig 1) with the embedded element of claim 1, wherein the element package comprises two or more elements (100,101).
Urashima does not disclose a distance between adjacent elements of the two or more elements is 30 μm to 300 μm.
Mikado (US 2013/0194764 A1) teaches of a substrate with the embedded element (Fig 1-4), wherein an element package (200,101a) comprises two or more elements (200a,200b), and a distance between adjacent elements of the two or more elements is 30 μm to 300 μm ([0106])
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate as disclosed by Urashima, wherein a distance between adjacent elements of the two or more elements is 30 μm to 300 μm as taught by Mikado, in order to reduce the size of the cavity, reduce occurrence of positional shifting of components, and increase a wiring region (Mikado, [0106]).
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Urashima (US 2007/0045815 A1) as applied to claim 1 above, and further in view of Lee (US 2014/0182896 A1).
Regarding Claim 8, Urashima discloses the limitations of the preceding claim and Urashima further discloses the substrate with the embedded element (Fig 1) of claim 1, wherein the core substrate (11) comprises a core inner surface (inner wall of 90 as seen in Fig 5) surrounding the cavity (90), wherein the substrate with the embedded element has a first point disposed on a surface of an element (an imaginary point on 100 adjacent the walls of 90) of the one or more elements and a second point (an imaginary point on the inner wall surface of 90 adjacent 100) disposed on the core inner surface.
Urashima does not disclose wherein a minimum distance between the first point and the second point is 20 μm to 150 μm.
Lee (US 2014/0182896 A1) teaches of a substrate with an embedded element (Fig 2), wherein a core substrate (140) comprises a core inner surface (inner wall of 145 at the callout 145) surrounding a cavity (145), wherein the substrate with the embedded element (110) has a first point (at a in Fig 2) disposed on a surface of an element (110) of the one or more elements and a second point (at a in Fig 2) disposed on the core inner surface, and wherein a minimum distance (“a” [0016-0017,0073-0075]) between the first point and the second point is 20 μm to 150 μm ([0016-0017,0073-0075]; 120 μm).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate as disclosed by Urashima, wherein the core substrate comprises a core inner surface surrounding the cavity, wherein the substrate with the embedded element has a first point disposed on a surface of an element of the one or more elements and a second point disposed on the core inner surface, and wherein a minimum distance between the first point and the second point is 20 μm to 150 μm as taught by Lee, in order to compensate for size variation of the embedded component, mounting position deviation and processing deviation (Lee, [0016-0017,0073-0075]).
Claim(s) 10 – 12 are rejected under 35 U.S.C. 103 as being unpatentable over Urashima (US 2007/0045815 A1) as applied to claim 1 above, and further in view of Jeong (US 2011/0048780 A1).
Regarding Claim 10, Urashima discloses the limitations of the preceding claim.
Urashima does not explicitly disclose the substrate with the embedded element of claim 1, wherein when observed from a cross-section of an in-plane direction of the substrate with the embedded element, a ratio of a value of an area of the cavity minus an area of the one or more elements based on the area of the cavity is 2.5% to 15%.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate as disclosed by Urashima, wherein when observed from a cross-section of an in-plane direction of the substrate with the embedded element, a ratio of a value of an area of the cavity minus an area of the one or more elements based on the area of the cavity is 2.5% to 15%, as motivated by Jeong (US 2011/0048780 A1) ([0048-0059]), in order to ensure proper insertion of the element into the cavity, reduce difficulty to secure space for circuit, and minimize warpage on the substrate, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding Claim 11, Urashima discloses the limitations of the preceding claim.
Urashima does not explicitly disclose the substrate with the embedded element of claim 1, wherein when observed from a cross-section of a thickness direction of the substrate with the embedded element, a ratio of a value of an area of the cavity minus an area of the one or more elements based on the area of the cavity is 2.5% to 15%.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate as disclosed by Urashima, wherein when observed from a cross-section of a thickness direction of the substrate with the embedded element, a ratio of a value of an area of the cavity minus an area of the one or more elements based on the area of the cavity is 2.5% to 15%, as motivated by Jeong (US 2011/0048780 A1) ([0048-0059]), in order to ensure proper insertion of the element into the cavity, reduce difficulty to secure space for circuit, and minimize warpage on the substrate, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding Claim 12,Urashima discloses the limitations of the preceding claim.
Urashima does not explicitly disclose the substrate with the embedded element of claim 1, wherein a ratio of a value of a volume of the cavity minus a volume of the one or more elements based on the volume of the cavity is 2% to 18%.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate as disclosed by Urashima, wherein a ratio of a value of a volume of the cavity minus a volume of the one or more elements based on the volume of the cavity is 2% to 18%, as motivated by Jeong (US 2011/0048780 A1) ([0048-0059]), in order to ensure proper insertion of the element into the cavity, reduce difficulty to secure space for circuit, and minimize warpage on the substrate, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
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/ROSHN K VARGHESE/Primary Examiner, Art Unit 2847
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