DETAILED ACTION
Claim Rejections - 35 USC § 102
1. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claim(s) 2 – 5, 7 – 9, 19, 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by FUKAYAMA et al. (20160079102).
With regard to claim 2, FUKAYAMA et al. disclose a method (for example, see figs. 3, 4), comprising:
receiving an image (for example, a camera 16 providing an image; for example, see paragraph [0018]) of a semiconductor die assembly (100, for example, see fig. 3);
detecting, in the image, a set of measurement features (alignment markers 54, 56, in fig. 3 below, functions as a set of measurement features) associated with a plurality of semiconductor dies (12, 20, 26), wherein at least two semiconductor dies (20, 26) of the plurality of semiconductor dies (12, 20, 26) comprise measurement features (alignment markers 54, 56 functions as a set of measurement features); and
determining distances (referred to as “D1” by examiner’s annotation shown in fig. 4 below) between a pair of adjacent semiconductor dies (20, 26) of the plurality of semiconductor dies (12, 20, 26) inherently based at least in part on determining distances (referred to as “D2” by examiner’s annotation shown in fig. 4 below; wherein the distance D2 is smaller than the distance D1 in order to secure the electrical connections between the bumps 24, 28 formed on both the pair of adjacent semiconductor dies 20, 26) between the measurement features (alignment markers 54, 56 functions as a set of measurement features) associated with the at least two semiconductor dies (20, 26).
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With regard to claim 3, FUKAYAMA et al. disclose the image is captured by an image capture device (16), the method further comprising: determining the distances (D2) between the measurement features (54, 56) based at least in part on a distance (a gap, formed between the semiconductor dies 20, 26 and the capture device 16, functioning as a distance) between the image capture device (16) and the semiconductor die assembly (the semiconductor die assembly including the semiconductor dies 20, 26).
With regard to claim 4, FUKAYAMA et al. disclose the measurement features (54, 56) are vertically aligned relative to each other.
With regard to claim 5, FUKAYAMA et al. disclose determining thicknesses of interconnects (the bumps 24, 28 function as interconnects) extending between each pair of adjacent semiconductor dies (20, 26) based at least in part on determining the distances (D1) between the measurement features (54, 56).
With regard to claim 7, FUKAYAMA et al. disclose the set of measurement features (54, 56) are closer to a first side (a top side of the semiconductor die 20 functions as a first side) of the at least two semiconductor dies (20, 26) than a second side (a bottom side of the semiconductor die 20 functions as a second side) of the at least two semiconductor dies (20, 26), and wherein the method further comprises:
receiving a second image (for example, a camera 16 providing an image; for example, see paragraph [0018]) of the semiconductor die assembly; detecting, in the second image, a second set of measurement features (the markers 52, 50 functioning as second measurement features) associated with the plurality of semiconductor dies (20, 26) closer to the second side (the bottom side of the semiconductor die 20 functions as the second side) than to the first side (the top side of the semiconductor die 20 functions as the first side), wherein the at least two semiconductor dies (12, 20) comprise measurement features (52, 50) of the second set of measurement features (the markers 52, 50);
determining distances (referred to as “D3” by examiner’s annotation shown in fig. 4 below) between a pair of adjacent semiconductor dies (12, 20) of the plurality of semiconductor dies (12, 20, 26) based at least in part on determining distances (referred to as “D4” by examiner’s annotation shown in fig. 4 below; wherein the distance D4 is smaller than the distance D3 in order to secure the electrical connections between the bumps 14, 22 formed on both the pair of adjacent semiconductor dies 12, 20) between the measurement features (52, 50) of the second set of measurement features (the markers 52, 50).
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With regard to claim 8, FUKAYAMA et al. disclose the first side (the top side) and the second side (the bottom side) of each semiconductor die (20) are parallel (parallel in horizontal direction).
With regard to claim 9, FUKAYAMA et al. disclose the first side (the top side) and the second side (the bottom side) of each semiconductor die (20) are perpendicular (in a vertical view, so the top side is perpendicular to the bottom side).
With regard to claim 19, FUKAYAMA et al. disclose a method (for example, see figs. 3, 4), comprising:
receiving an image (for example, a camera 16 providing an image; for example, see paragraph [0018]) of a semiconductor die assembly (100, for example, see fig. 3);
detecting, in the image, a set of measurement features (alignment markers 54, 56, in fig. 3 below, functions as a set of measurement features) associated with a plurality of semiconductor dies (12, 20, 26),
wherein each semiconductor die (20, 26) comprises measurement features (alignment markers 54, 56 functions as a set of measurement features); and
determining, for each pair of semiconductor dies (20, 26) of the plurality of semiconductor dies (12, 20, 26), a distance (referred to as “D1” by examiner’s annotation shown in fig. 4 below) between a top semiconductor die (26) of a pair of semiconductor dies (20, 26) and a bottom semiconductor die (20) of the pair of semiconductor dies (20, 26) inherently based at least in part on determining a distance (referred to as “D2” by examiner’s annotation shown in fig. 4 below; wherein the distance D2 must be smaller than the distance D1 in order to secure the electrical connections between the bumps 24, 28 formed on both the pair of adjacent semiconductor dies 20, 26) between the measurement features (alignment markers 54, 56 functions as a set of measurement features) associated with the top semiconductor die (26) and the measurement features (54, 56) associated with the bottom semiconductor die (20).
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With regard to claim 20, FUKAYAMA et al. disclose determining, for each pair of semiconductor dies (20, 26), a thickness of interconnects (the bumps 24, 28 function as interconnects) extending between the top semiconductor die (26) and the bottom semiconductor die (20) based at least in part on determining the distances (D1) between the measurement features (54, 56) associated with the top semiconductor die (26) and the measurement features (54, 56) associated with the bottom semiconductor die (20).
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 6, 21 are rejected under 35 U.S.C. 103 as being unpatentable over FUKAYAMA et al. (20160079102) in view of Lee (7741652).
With regard to claim 6, FUKAYAMA et al. do not clearly disclose determining a degree of warpage between each pair of adjacent semiconductor dies based at least in part on determining the distances between the measurement features.
However, Lee discloses determining a degree (any degree is a degree) of warpage between each pair of adjacent semiconductor dies (100, 400) based at least in part on determining the distances between the measurement features (referred to as “10A” and “10B” by examiner’s annotation shown in fig. 3 below; wherein the measurement features 10A, 10B are portions of the alignment feature 10). (for example, see column 1, lines 19 – 21, column 5, lines 1 – 5, fig. 3).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the FUKAYAMA et al.’s device to have determining a degree of warpage between each pair of adjacent semiconductor dies based at least in part on determining the distances between the measurement features as taught by Lee in order to enhance more flexible package and alignment efficiency for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 21, FUKAYAMA et al. do not clearly disclose determining, for each pair of semiconductor dies a degree of warpage between the top semiconductor die and the bottom semiconductor die based at least in part on determining the distance between the measurement features associated with the top semiconductor die and the measurement features associated with the bottom semiconductor die.
However, Lee discloses determining, for each pair of semiconductor dies a degree (any degree is a degree) of warpage between the top semiconductor die (400) and the bottom semiconductor die (100) based at least in part on determining the distance between the measurement features (referred to as “10A” and “10B” by examiner’s annotation shown in fig. 3 below; wherein the measurement features 10A, 10B are portions of the alignment feature 10) associated with the top semiconductor die (400) and the measurement features (10A, 10B) associated with the bottom semiconductor die (100). (for example, see column 1, lines 19 – 21, column 5, lines 1 – 5, fig. 3).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the FUKAYAMA et al.’s device to have determining, for each pair of semiconductor dies a degree of warpage between the top semiconductor die and the bottom semiconductor die based at least in part on determining the distance between the measurement features associated with the top semiconductor die and the measurement features associated with the bottom semiconductor die as taught by Lee in order to enhance more flexible package and alignment efficiency for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Allowable Subject Matter
5. Claims 10 - 18 are allowable over the prior art of record because none of these references disclose or can be combined to yield the claimed invention such as forming, based at least in part on forming the conductive pads, measurement features spaced apart from a side of a semiconductor die by a distance of about 2000 µm to 5000 µm; and stacking the plurality of semiconductor dies based at least in part on forming the measurement features as recited in claim 10.
Response to Arguments
6. Applicant’s arguments filed 07/21/26 have been fully considered but they are not persuasive.
It is argued, at pages of the remarks, that “Fukayama does not disclose at all discuss any vertical measurement or there are no figures in Fukayama, or any accompanying description, that show or discuss a dimension or distance between chips”. However, figs. 3, 4 of Fukayama does show determining distances between a pair of adjacent semiconductor dies (20, 26) of the plurality of semiconductor dies (12, 20, 26) inherently based at least in part on determining distances (referred to as “D2” by examiner’s annotation shown in fig. 4 below; wherein the distance D2 must be smaller than the distance D1 in order to secure the electrical connections between the bumps 24, 28 formed on both the pair of adjacent semiconductor dies 20, 26) between the measurement features (alignment markers 54, 56 functions as a set of measurement features) associated with the at least two semiconductor dies (20, 26).
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Conclusion
7. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812
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