DETAILED ACTION
1. Applicant’s communication filed on 03/10/26 has been carefully reconsidered by the examiner. The previous restriction/election action is accordingly withdrawn based on “no burden to examine the claims”, and all original claims will be examined.
Specification
2. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim(s) 3 – 5, 7 – 9, 19, 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by FUKAYAMA et al. (20160079102).
With regard to claim 2, FUKAYAMA et al. disclose a method (for example, see figs. 3, 4), comprising:
receiving an image (for example, a camera 16 providing an image; for example, see paragraph [0018]) of a semiconductor die assembly (100, for example, see fig. 3);
detecting, in the image, a set of measurement features (alignment markers 54, 56, in fig. 3 below, functions as a set of measurement features) associated with a plurality of semiconductor dies (12, 20, 26), wherein at least two semiconductor dies (20, 26) of the plurality of semiconductor dies (12, 20, 26) comprise measurement features (alignment markers 54, 56 functions as a set of measurement features); and
determining distances (referred to as “D1” by examiner’s annotation shown in fig. 4 below) between a pair of adjacent semiconductor dies (20, 26) of the plurality of semiconductor dies (12, 20, 26) based at least in part on determining distances (referred to as “D2” by examiner’s annotation shown in fig. 4 below; wherein the distance D2 is smaller than the distance D1 in order to secure the electrical connections between the bumps 24, 28 formed on both the pair of adjacent semiconductor dies 20, 26) between the measurement features (alignment markers 54, 56 functions as a set of measurement features) associated with the at least two semiconductor dies (20, 26).
PNG
media_image1.png
463
597
media_image1.png
Greyscale
PNG
media_image2.png
351
798
media_image2.png
Greyscale
With regard to claim 3, FUKAYAMA et al. disclose the image comprises an image capture device (16), the method further comprising: determining the distances (D2) between the measurement features (54, 56) based at least in part on a distance (a gap, formed between the semiconductor dies 20, 26 and the capture device 16, functioning as a distance) between the image capture device (16) and the semiconductor die assembly (the semiconductor die assembly including the semiconductor dies 20, 26).
With regard to claim 4, FUKAYAMA et al. disclose the measurement features (54, 56) are vertically aligned relative to each other.
With regard to claim 5, FUKAYAMA et al. disclose determining thicknesses of interconnects (the bumps 24, 28 function as interconnects) extending between each pair of adjacent semiconductor dies (20, 26) based at least in part on determining the distances (D1) between the measurement features (54, 56).
With regard to claim 7, FUKAYAMA et al. disclose the set of measurement features (54, 56) are closer to a first side (a top side of the semiconductor die 20 functions as a first side) of the at least two semiconductor dies (20, 26) than a second side (a bottom side of the semiconductor die 20 functions as a second side) of the at least two semiconductor dies (20, 26), and wherein the method further comprises:
receiving a second image (for example, a camera 16 providing an image; for example, see paragraph [0018]) of the semiconductor die assembly; detecting, in the second image, a second set of measurement features (the markers 52, 50 functioning as second measurement features) associated with the plurality of semiconductor dies (20, 26) closer to the second side (the bottom side of the semiconductor die 20 functions as the second side) than to the first side (the top side of the semiconductor die 20 functions as the first side), wherein the at least two semiconductor dies (12, 20) comprise measurement features (52, 50) of the second set of measurement features (the markers 52, 50);
determining distances (referred to as “D3” by examiner’s annotation shown in fig. 4 below) between a pair of adjacent semiconductor dies (12, 20) of the plurality of semiconductor dies (12, 20, 26) based at least in part on determining distances (referred to as “D4” by examiner’s annotation shown in fig. 4 below; wherein the distance D4 is smaller than the distance D3 in order to secure the electrical connections between the bumps 14, 22 formed on both the pair of adjacent semiconductor dies 12, 20) between the measurement features (52, 50) of the second set of measurement features (the markers 52, 50).
PNG
media_image3.png
365
797
media_image3.png
Greyscale
With regard to claim 8, FUKAYAMA et al. disclose the first side (the top side) and the second side (the bottom side) of each semiconductor die (20) are parallel (parallel in horizontal direction).
With regard to claim 9, FUKAYAMA et al. disclose the first side (the top side) and the second side (the bottom side) of each semiconductor die (20) are perpendicular (in a vertical view, so the top side is perpendicular to the bottom side).
With regard to claim 19, FUKAYAMA et al. disclose a method (for example, see figs. 3, 4), comprising:
receiving an image (for example, a camera 16 providing an image; for example, see paragraph [0018]) of a semiconductor die assembly (100, for example, see fig. 3);
detecting, in the image, a set of measurement features (alignment markers 54, 56, in fig. 3 below, functions as a set of measurement features) associated with a plurality of semiconductor dies (12, 20, 26),
wherein each semiconductor die (20, 26) comprises measurement features (alignment markers 54, 56 functions as a set of measurement features); and
determining, for each pair of semiconductor dies (20, 26) of the plurality of semiconductor dies (12, 20, 26), a distance (referred to as “D1” by examiner’s annotation shown in fig. 4 below) between a top semiconductor die (26) of a pair of semiconductor dies (20, 26) and a bottom semiconductor die (20) of the pair of semiconductor dies (20, 26) based at least in part on determining a distance (referred to as “D2” by examiner’s annotation shown in fig. 4 below; wherein the distance D2 must be smaller than the distance D1 in order to secure the electrical connections between the bumps 24, 28 formed on both the pair of adjacent semiconductor dies 20, 26) between the measurement features (alignment markers 54, 56 functions as a set of measurement features) associated with the top semiconductor die (26) and the measurement features (54, 56) associated with the bottom semiconductor die (20).
PNG
media_image1.png
463
597
media_image1.png
Greyscale
PNG
media_image2.png
351
798
media_image2.png
Greyscale
With regard to claim 20, FUKAYAMA et al. disclose determining, for each pair of semiconductor dies (20, 26), a thickness of interconnects (the bumps 24, 28 function as interconnects) extending between the top semiconductor die (26) and the bottom semiconductor die (20) based at least in part on determining the distances (D1) between the measurement features (54, 56) associated with the top semiconductor die (26) and the measurement features (54, 56) associated with the bottom semiconductor die (20).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 6, 21 are rejected under 35 U.S.C. 103 as being unpatentable over FUKAYAMA et al. (20160079102) in view of Lee (7741652).
With regard to claim 6, FUKAYAMA et al. do not clearly disclose determining a degree of warpage between each pair of adjacent semiconductor dies based at least in part on determining the distances between the measurement features.
However, Lee discloses determining a degree (any degree is a degree) of warpage between each pair of adjacent semiconductor dies (100, 400) based at least in part on determining the distances between the measurement features (referred to as “10A” and “10B” by examiner’s annotation shown in fig. 3 below; wherein the measurement features 10A, 10B are portions of the alignment feature 10). (for example, see column 1, lines 19 – 21, column 5, lines 1 – 5, fig. 3).
PNG
media_image4.png
456
747
media_image4.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the FUKAYAMA et al.’s device to have determining a degree of warpage between each pair of adjacent semiconductor dies based at least in part on determining the distances between the measurement features as taught by Lee in order to enhance more flexible package and alignment efficiency for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 21, FUKAYAMA et al. do not clearly disclose determining, for each pair of semiconductor dies a degree of warpage between the top semiconductor die and the bottom semiconductor die based at least in part on determining the distance between the measurement features associated with the top semiconductor die and the measurement features associated with the bottom semiconductor die.
However, Lee discloses determining, for each pair of semiconductor dies a degree (any degree is a degree) of warpage between the top semiconductor die (400) and the bottom semiconductor die (100) based at least in part on determining the distance between the measurement features (referred to as “10A” and “10B” by examiner’s annotation shown in fig. 3 below; wherein the measurement features 10A, 10B are portions of the alignment feature 10) associated with the top semiconductor die (400) and the measurement features (10A, 10B) associated with the bottom semiconductor die (100). (for example, see column 1, lines 19 – 21, column 5, lines 1 – 5, fig. 3).
PNG
media_image4.png
456
747
media_image4.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the FUKAYAMA et al.’s device to have determining, for each pair of semiconductor dies a degree of warpage between the top semiconductor die and the bottom semiconductor die based at least in part on determining the distance between the measurement features associated with the top semiconductor die and the measurement features associated with the bottom semiconductor die as taught by Lee in order to enhance more flexible package and alignment efficiency for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
7. Claims 10 - 15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over PARK et al. (20170025384) in view of Sakatani (10097734).
With regard to claim 10, PARK et al. disclose a method of manufacturing a semiconductor die assembly (for example, see a semiconductor die assembly forming in fig. 6), comprising:
forming, for each semiconductor die (100) of a plurality of semiconductor dies (100) associated with the semiconductor die assembly, conductive pads (80, 82) electrically coupled with through silicon vias (30) extending through the plurality of semiconductor dies (100);
forming, based at least in part on forming the conductive pads (80, 82), measurement features (alignment marks AK function as measurement features) spaced apart from a side (a top surface side) of a semiconductor die (100); and
stacking the plurality of semiconductor dies (100) based at least in part on forming the measurement features (alignment marks AK function as measurement features; for example, paragraphs [0065], [0110], [0119]).
PNG
media_image5.png
482
649
media_image5.png
Greyscale
PARK et al. does not clearly disclose measurement features spaced apart from a side of a die (100) by a distance of about 2000 μm.
However, Kunikiyo et al. disclose measurement features (alignment marks 84 function as measurement features) spaced apart and from a side (the edge of the sheet 80) of a die (the sheet 80, including image area 81, functions a die) by a distance of about 2 mm = 2000 μm. (for example, see column 6, lines 14 – 17, fig. 3).
PNG
media_image6.png
667
564
media_image6.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Park et al.’s device to have measurement features spaced apart from a side of a die by a distance of about 2000 μm as taught by Kunikiyo et al. in order to reduce erroneous winding of the semiconductor die for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 11, PARK et al. disclose bonding, based at least in part on stacking the plurality of semiconductor dies (100), the conductive pads (82) of a first semiconductor die (a top semiconductor die 100 functions a first semiconductor die) of the plurality of semiconductor dies (100) with corresponding conductive pads (80) of a second semiconductor die (a bottom semiconductor die 100 functions a second semiconductor die) of the plurality of semiconductor dies (100), the first and second semiconductor dies (100) functions as a pair of adjacent semiconductor dies.
PNG
media_image5.png
482
649
media_image5.png
Greyscale
With regard to claim 12, PARK et al. disclose forming a plurality of interconnects (154) between a pair of adjacent semiconductor dies (100) of the plurality of semiconductor dies (100) based at least in part on stacking the plurality of semiconductor dies (100).
With regard to claim 13, PARK et al. disclose forming a barrier material (a molding layer 220 functions as a barrier material) at least partially surrounding each of the conductive pads (80, 82), wherein forming the plurality of interconnects (154) is based at least in part on forming the barrier material (220).
With regard to claim 14, PARK et al. disclose stacking the plurality of semiconductor dies (100) comprises vertically aligning the measurement features (AK).
With regard to claim 15, PARK et al. disclose the measurement features (AK) are electrically isolated (isolated from one another; for example, the measurement features AK, formed on the top semiconductor die 100, is isolated from the bottom semiconductor die 100; or the measurement features AK, formed on the bottom semiconductor die 100, is isolated from the top semiconductor die 100) from the plurality of semiconductor dies (100).
With regard to claim 17, PARK et al. disclose each measurement feature (AK) of the measurement features (AK) are spaced apart from a side (a top surface side) of a respective semiconductor die (one of the semiconductors dies 100) by a same distance (any distance be a same distance, as shown in fig. 6).
8. Claims 16, 18 are rejected under 35 U.S.C. 103 as being unpatentable over PARK et al. (20170025384) in view of Sakatani (10097734) and further in view of Yan et al. (2020/0159133).
With regard to claims 16, 18, PARK et al. and Sakatani do not clearly disclose the conductive pads and the measurement features comprise a same metal material wherein the conductive pads and the measurement features comprise a same thickness.
However, Yan et al. disclose the conductive pads (referred to as “416B” and “428B” by examiner’s annotation shown in fig. 4 below) and the measurement features (referred to as “416A” and “428a” by examiner’s annotation shown in fig. 4 below) comprise a same metal material wherein the conductive pads (416B, 428B) and the measurement features (416A, 428A) comprise a same thickness. (for example, see fig. 3).
PNG
media_image7.png
612
771
media_image7.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the PARK et al. and Sakatani’s device to have the conductive pads and the measurement features comprise a same metal material wherein the conductive pads and the measurement features comprise a same thickness as taught by Yan et al. in order to enhance alignment efficiency for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TAN N TRAN/
Primary Examiner, Art Unit 2812
Prosecution Insights