Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 15, and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Anderson et al, US 20120112287.
Regarding claim 1, Anderson discloses : A semiconductor device comprising: a substrate(Fig. 9a, #100); a shallow trench isolation (STI) layer formed on the substrate(#105); and a first gate(#130a), a second gate(#130b), and a gate strap connecting the first gate to the second gate(#130c connects #130a and #130b [0015]), wherein the gate strap is formed in the STI layer(#130c below a top surface of #105 formed in #120[0020]).
Regarding claim 2, Anderson discloses : The semiconductor device of claim 1, wherein a top surface of the gate strap is below a top surface of the STI layer(#130c below a top surface of #105 formed in #120[0020]).
Regarding claim 15, Anderson discloses : An electronic device comprising: a semiconductor device including: a substrate(Fig. 9a, #100; a shallow trench isolation (STI) layer formed on the substrate(#105); and a first gate(#130a), a second gate(#130b), and a gate strap connecting the first gate to the second gate(#130c connects #130a and #130b [0015]), wherein the gate strap is formed in the STI layer(#130c below a top surface of #105 formed in #120[0020]).
Regarding claim 16, Anderson discloses : The electronic device of claim 15, wherein a top surface of the gate strap is below a top surface of the STI layer(#130c below a top surface of #105 formed in #120[0020]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-9, 13, 14, and 17-20 is/are rejected under 35 U.S.C. 103 as being anticipated by Anderson et al, US 20120112287 in view of Kim et al, US 20240113163.
Regarding claim 3, Anderson discloses : The semiconductor device of claim 1.
Anderson does not disclose : further comprising a first gate contact formed in contact with only the first gate.
However, in the same field of endeavor, Kim teaches : further comprising a first gate contact formed in contact with only the first gate(Fig. 14b, #GC connected to only the right #GC).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Kim to provide a single gate contact to a gate of Anderson. Selecting only the first gate for contact is routine design choice in the strap connection two gate arrangement of Anderson, in which both gates are already electrically connected through the strap.
Regarding claim 4, Anderson as modified by Kim discloses : The semiconductor device of claim 3.
Kim teaches : further comprising a sacrificial protective cap formed in contact with only the second gate(Fig. 14b, #GP in contact with #GE that are not in contact with #GC).
Regarding claim 5, Anderson as modified by Kim discloses : The semiconductor device of claim 3.
Kim teaches : further comprising a source/drain epitaxial layer formed on the substrate(Fig. 14b #SD2 formed on #100).
Regarding claim 6, Anderson as modified by Kim discloses : The semiconductor device of claim 5.
Kim teaches : further comprising a source/drain contact formed on the source/drain epitaxial layer(Fig. 14b, #AC formed in contact with #SD2).
Regarding claim 7, Anderson as modified by Kim discloses : The semiconductor device of claim 6.
Kim teaches : wherein a top surface of the source/drain contact is below a top surface of the gate contact(Fig. 14b, top surface of #AC below a top surface of #GC).
Regarding claim 8, Anderson as modified by Kim discloses : The semiconductor device of claim 6.
Kim teaches : further comprising a dielectric spacer layer formed around and in contact with the first gate contact(Fig. 14c, #GS), wherein the dielectric spacer layer is formed between the first gate contact and the source/drain contact to electrically isolate the first gate contact from the source/drain contact(#GS between #GC and #AC and may include a silicon-containing dielectric material [0106]).
Regarding claim 9, Anderson as modified by Kim discloses : The semiconductor device of claim 8.
Kim teaches : wherein the dielectric spacer layer is also in contact with the source/drain contact(Fig. 14b, #GS in contact with #AC).
Regarding claim 13, Anderson as modified by Kim discloses : The semiconductor device of claim 3.
Kim teaches : further comprising: a third gate(Fig. 19a, three #GE shown); a second gate contact formed in contact with the third gate(#GC in contact with #GE in the left and middle); a first metal layer contacts formed in contact with the first gate contact(#M1_I in contact with #GC on the left); and a second metal layer contact formed in contact with the second gate contact(#ML_I in contact with #GC in the middle).
Regarding claim 14, Anderson as modified by Kim discloses : The semiconductor device according to claim 3.
Kim teaches : wherein the first gate contact is formed to a width so as to not cover the second gate(Fig. 14a, #GC in the middle not covering #GE on the right).
Regarding claim 17, Anderson discloses : The electronic device of claim 15.
Anderson does not disclose : further comprising a gate contact formed in contact with only the first gate.
However, in the same field of endeavor, Kim teaches : further comprising a gate contact formed in contact with only the first gate(Fig. 14b, #GC connected to only the right #GC).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Kim to provide a single gate contact to a gate of Anderson. Selecting only the first gate for contact is routine design choice in the strap connection two gate arrangement of Anderson, in which both gates are already electrically connected through the strap.
Regarding claim 18, Anderson as modified by Kim discloses : The electronic device of claim 17.
Kim teaches : further comprising a sacrificial protective cap formed in contact with only the second gate(Fig. 14b, #GP in contact with #GE that are not in contact with #GC).
Regarding claim 19, Anderson as modified by Kim discloses : The electronic device of claim 17.
Kim teaches : further comprising a source/drain epitaxial layer formed on the substrate(Fig. 14b #SD2 formed on #100).
Regarding claim 20, Anderson as modified by Kim discloses : The electronic device of claim 19.
Kim teaches : further comprising a source/drain contact formed on the source/drain epitaxial layer(Fig. 14b, #AC formed in contact with #SD2).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being anticipated by Anderson et al, US 20120112287 in view Ando et al, US 9425279.
Regarding claim 10, Anderson discloses : The semiconductor device of claim 1.
Anderson does not disclose : wherein the gate strap includes a high-κ dielectric layer, a work function metal layer in contact with the high-κ dielectric layer, and a gate metal fill layer in contact with the work function metal layer.
However, in the same field of endeavor, Ando teaches : wherein the gate strap includes a high-κ dielectric layer(Fig. 6b, #112 high-k layer), a work function metal layer in contact with the high-κ dielectric layer(#116 work function metal layer in contact with #112), and a gate metal fill layer in contact with the work function metal layer(#120 Col. 6, line 55-65).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of a gate contact with work function metal layer and high-k dielectric layer to the strap of Anderson to reduce the variation of threshold voltage (Ando, Col. 2 line 12-26).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being anticipated by Anderson et al, US 20120112287 in view of Kim et al, US 20240113163 in further view of Agarwal et al, US 20240071985.
Regarding claim 11, Anderson as modified by Kim discloses : The semiconductor device of claim 3.
Anderson as modified by Kim does not disclose : further comprising a back end of line (BEOL) layer and a middle of line (MOL) layer, wherein the first gate contact is formed in the MOL layer.
However, in the same field of endeavor, Agarwal teaches : further comprising a back end of line (BEOL) layer and a middle of line (MOL) layer, wherein the first gate contact is formed in the MOL layer(Gate contacts formed in middle of line layers with additional conductive elements in back end of line [0026]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to form a gate contact in the middle of line layer because the known technique of forming interconnects in a semiconductor device was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being anticipated by Anderson et al, US 20120112287 in view of Xie et al, US 20230124681.
Regarding claim 12, Anderson discloses : The semiconductor device of claim 1.
Anderson does not disclose : wherein the first gate and the second gate are formed as a nanosheet stack structure that includes alternating layers of a work function metal layer and a semiconductor layer.
However, in the same field of endeavor, Xie teaches : wherein the first gate and the second gate are formed as a nanosheet stack structure that includes alternating layers of a work function metal layer and a semiconductor layer(Fig. 4, #410 high-k metal gate stack with replacement metal gate to include work function metal layers [0043]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Xie to Anderson to form the first and second gates of Anderson as nanosheet per Xie since nanosheets was established successor technology in the art, yielding predictable results.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : US 20200111799 : Gate structure in shallow trench isolation
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/D.T./Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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