Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 8, and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 5, lines 8-10 recite the phrase “and the third power chip is located between the first conductive portion and the second conductive portion in the first direction.”. This phrase renders the claim indefinite, as when viewing Fig. 3 of the instant application, the third power chip is not located between the first and second conductive portions in the first direction, but rather diagonally adjacent to these respective regions. Additionally, in the first direction, the first conductive portion and the second conductive portion are regions of the same structure within the device and are therefore directly adjacent to each other with no intervening power chip. According to Fig. 3 of the instant application, as best understood by the examiner, the third power chip 13 is located between the first conductive portion of the first conductive region 21 and the first conductive portion of the second conductive region 31, in the second direction. Therefore, the phrase from claim 5 will be interpreted as the following:
“… the third power chip 8 is located between the first conductive portion of the first conductive region 21 and the first conductive portion of the second conductive region 31, in the second direction.”
Regarding Claim 8: Claim 8 recites the limitation “wherein the first conductive branch…”. In line 7 of the claim. There is insufficient antecedent basis for this limitation in the claim. “the first conductive branch” should be introduced in a fashion similar to the following suggestion:
“…wherein a first conductive branch of the plurality of first conductive branches is located…”
Regarding Claim 9: Claim 9 recites the limitation “wherein the second conductive branch…”. In line 10 of the claim. There is insufficient antecedent basis for this limitation in the claim. “the second conductive branch” should be introduced in a fashion similar to the following suggestion:
“…wherein a second conductive branch of the plurality of second conductive branches is located…”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 15-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2023/0056722 A1 Bergmann et al (herein “Bergmann”).
Regarding Claim 1, Bergmann discloses:
A semiconductor power module (#1, see generally the embodiment shown in Fig. 8 showing power module and various conductive regions), comprising:
a substrate (#2, [0040]) having a first direction (#9, y-direction) and a second direction (#10, x-direction) that are orthogonal to each other;
a first conductive region (#7, see annotated Fig. 8 below),
a second conductive region (#8, see annotated Fig. 8 below),
a third conductive region (#4: 4’ and 4’’, [0048], see annotated Fig. 8 below), and
a fourth conductive region (#5 and #6, see annotated Fig. 8 below) that are disposed on the substrate (#2) and that are spaced apart from each other,
wherein the first conductive region (#7) and the second conductive region (#8) extend along the first direction (y-direction) of the substrate (#2) and are arranged along the second direction (x-direction) of the substrate (#2), the third conductive region (#4) and the fourth conductive region (#6) are located between the first conductive region (#7) and the second conductive region (#8) and are arranged along the first direction (y-direction), the first conductive region (#7), the second conductive region (#8) and the third conductive region (#4) are configured to transmit a direct current signal ([0003], [0024], [0049], [0052]), and the fourth conductive region (#5, #6) is configured to transmit an alternating current signal ([0003], [0024], [0049], [0052]); and
at least one first power chip (#11-14), at least one second power chip (#23-26), and at least one third power chip (#15-18 and #19-21), the first power chip (#11-14) is electrically connected to each of the first conductive region (#7) and the fourth conductive region (#5, #6), the second power chip (#23-26) is electrically connected to each of the second conductive region (#8) and the fourth conductive region (#4), and the third power chip (#15-18 and #19-21) is electrically connected to each of the fourth conductive region (#5, #6) and the third conductive region (#4).
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Bergmann Fig. 8 – Annotated by Examiner
Regarding Claim 2, Bergmann discloses: The semiconductor power module according to claim 1,
Bergmann further discloses:
wherein the first conductive region (#7), the second conductive region (#8), and the third conductive region (#4) are configured to receive the direct current signal ([0003], [0024], [0049], [0052]), and the fourth conductive region (#5, #6) is configured to output the alternating current signal ([0003], [0024], [0049], [0052]).
Regarding Claim 3, Bergmann discloses: The semiconductor power module according to claim 1,
Bergmann further discloses:
wherein the substrate has a first edge (left edge), a second edge (top edge), a third edge (right edge), and a fourth edge (bottom edge) that are connected in a sequential and head to tail manner, the first edge and the third edge are disposed opposite to each other in the second direction, and the second edge and the fourth edge are disposed opposite to each other in the first direction; and
wherein the first conductive region (#7) is disposed adjacent to each of the first edge, the second edge, and the fourth edge, the second conductive region (#8) is disposed adjacent to each of the third edge, the second edge and the fourth edge, the third conductive region (#4) is disposed adjacent to the second edge, and the fourth conductive region (#5, #6) is disposed adjacent to the fourth edge.
Regarding Claim 4, Bergmann discloses: The semiconductor power module according to claim 2,
Bergmann further discloses:
wherein the third conductive region (#4) extends between the first conductive region (#7) and the second conductive region (#8) along the second direction (x-direction) and is disposed adjacent to one end of the first conductive region (#7) and one end of the second conductive region (#8) that receive the direct current signal; and
the fourth conductive region (#5, #6) extends between the first conductive region (#7) and the second conductive region (#8) along the first direction (y-direction) and is disposed adjacent to another end of the first conductive region (#7) and another end of the second conductive region (#8).
Regarding Claim 15, Bergmann discloses: The semiconductor power module according to claim 1,
Bergmann further discloses:
wherein a plurality of third power chips (#15-18, #19-21) are comprised and the plurality of the third power chips (#15-18, #19-21) are arranged in the first direction (y-direction) or the second direction (y-direction).
Regarding Claim 16, Bergmann discloses: The semiconductor power module according to claim 1,
Bergmann further discloses:
wherein the first power chip (#11-14) and the second power chip (#23-26) are arranged in the second direction (x-direction); and
a plurality of first power chips (#11-14) are comprised, a plurality of second power chips (#23-26) are comprised, and the plurality of the first power chips (#11-14) are arranged in the same direction as that of the plurality of the second power chips (#23-26).
Regarding Claim 17, Bergmann discloses: The semiconductor power module according to claim 1,
Bergmann further discloses:
wherein the first power chip (#11-14) and the third power chip (#15-18, #19-21) are arranged along the first direction (y-direction); and
the second power chip (#23-26) and the third power chip (#15-18, #19-21) are arranged along the first direction (y-direction).
Regarding Claim 18, Bergmann discloses: The semiconductor power module according to claim 1,
Bergmann further discloses:
wherein a sum of the number of the at least one first power chip (#11-14) and the number of the at least one second power chip (#23-26) is equal to (see Fig. 8) the number of the at least one third power chip (#15-18, #19-21).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5-14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0056722 A1 Bergmann et al in view of US 20210280555 A1 Murata et al (herein “Murata”).
Regarding Claim 5, Bergmann discloses: The semiconductor power module according to claim 2,
Bergmann further discloses:
wherein each of the first conductive region (#7) and the second conductive region (#8) comprises:
a first conductive portion (see annotated Fig. 8 above), a second conductive portion (see annotated Fig. 8 above), and a third conductive portion (see annotated Fig. 8 above) that are connected in sequence along the first direction (y-direction), wherein the first conductive portion (see annotated Fig. 8 above) is configured to receive the direct current signal, the first power chip (#56, left) is connected to the third conductive portion (see annotated Fig. 8 above) of the first conductive region (#7), the second power chip (#56, right) is connected to the third conductive portion (see annotated Fig. 8 above) of the second conductive region (#8), the third power chip (#15-18, #19-21) is located between the first conductive portion of the first conductive region (see annotated Fig. 8 above) and the first conductive portion of the second conductive region (see annotated Fig. 8 above), in the second direction (x-direction).
Note, see 112(b) rejection of claim 5 above.
Bergmann does not explicitly disclose:
the third conductive portion protrudes, in comparison to the second conductive portion, towards the fourth conductive region
However, in analogous art, Murata teaches:
See generally Fig. 1 and Fig. 7. See also [0059]-[0062].
the third conductive portion (see annotated Fig. 1 below) protrudes, in comparison to the second conductive portion (see annotated Fig. 1 below), towards the fourth conductive region (#24).
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Murata Fig. 1 – Annotated by Examiner
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Murata to the device disclosed by Bergmann and form the first and second conductive regions such that the respective third conductive portions protrude towards the fourth conductive portion. Paragraph [0061] discloses the disclosed wiring pattern is formed in order to shorten/reduce current path, which in turn would lower the electrical resistance within the device during operation. Therefore, a person of ordinary skill in the art would form the device in this manner and layout in order to optimize/improve the performance of the device.
Regarding Claim 6, Bergmann in view of Murata discloses: The semiconductor power module according to claim 5,
Murata further teaches:
wherein an edge of the second conductive portion (see annotated Fig. 1 above) of the first conductive region (#26) that faces away from the third conductive region (#23) is flush with an edge of the third conductive portion (see annotated Fig. 1 above) of the first conductive region (#26) that faces away from the fourth conductive region (#24), and the third conductive portion (see annotated Fig. 1 above) of the first conductive region (#26) has a width that is greater than a width of the second conductive portion (see annotated Fig. 1 above) of the first conductive region (#26); and
an edge of the second conductive portion (see annotated Fig. 1 above) of the second conductive region (#25) that faces away from the third conductive region (#23) is flush with an edge of the third conductive portion (see annotated Fig. 1 above) of the second conductive region (#25) that faces away from the fourth conductive region (#24), and the third conductive portion (see annotated Fig. 1 above) of the second conductive region (#25) has a width that is greater than a width of the second conductive portion (see annotated Fig. 1 above) of the second conductive region (#25).
Regarding Claim 7, Bergmann in view of Murata discloses: The semiconductor power module according to claim 5,
Murata further teaches:
wherein an edge of the first conductive portion (see annotated Fig. 1 above) of the first conductive region (#26) that faces away from the third conductive region (#23) is flush with an edge of the second conductive portion (see annotated Fig. 1 above) of the first conductive region (#26) that faces away from the fourth conductive region (#24), and the first conductive portion (see annotated Fig. 1 above) of the first conductive region (#26) has a width that is greater than a width of the second conductive portion (see annotated Fig. 1 above) of the first conductive region (#26); and
an edge of the first conductive portion (see annotated Fig. 1 above) of the second conductive region (#25) that faces away from the third conductive region (#23) is flush with an edge of the second conductive portion (see annotated Fig. 1 above) of the second conductive region (#25) that faces away from the fourth conductive region (#24), and the first conductive portion (see annotated Fig. 1 above) of the second conductive region (#25) has a width that is greater than a width of the second conductive portion (see annotated Fig. 1 above) of the second conductive region (#25).
Regarding Claim 8, Bergmann in view of Murata discloses: The semiconductor power module according to claim 5,
Bergmann further discloses:
wherein the third conductive region (#4) comprises:
a first converging conductive portion (horizontal portion of #4) extending in the second direction (x-direction) and configured to receive the direct current signal (0003], [0024], [0049], [0052]); and
a plurality of first conductive branches (#4’, #4’’) connected with the first converging conductive portion (horizontal portion of #4) and extending towards the fourth conductive region (#5, #6) in the first direction (y-direction);
wherein a first conductive branch (#4’) of the plurality of first conductive branches (#4’, #4’’) is located between the second conductive portion (see annotated Fig. 8 above) of the first conductive region (#7) and the second conductive portion (see annotated Fig. 8 above) of the second conductive region (#8), and the third power chip (#15-18, #19-21) is connected to the first conductive branch (#4’) of the third conductive region (#4).
Note, see 112(b) rejection of claim 8 above.
Regarding Claim 9, Bergmann in view of Murata discloses: The semiconductor power module according to claim 8,
Bergmann further discloses:
wherein the fourth conductive region (#5, #6) comprising:
a second converging conductive portion (horizontal portion of #5, #6) extending in the first direction (y-direction) and configured to output the alternating current signal (0003], [0024], [0049], [0052]);
a plurality of second conductive branches (#5, #6) connected with the second converging conductive portion (horizontal portion of #5, #6) and extending towards the third conductive region (#4) in the first direction (y-direction);
wherein the second converging conductive portion (horizontal portion of #5, #6) is located between the third conductive portion (see annotated Fig. 8 above) of the first conductive region (#7) and the third conductive portion (see annotated Fig. 8 above) of the second conductive region (#8), the first power chip (#11-14) and the second power chip (#23-26) are connected to the second converging conductive portion (horizontal portion of #5, #6) of the fourth conductive region (#4), wherein a second conductive branch (#5) of the plurality of second conductive branches (#5, #6) is located between the second conductive portion (see annotated Fig. 8 above) of the first conductive region (#7) and the second conductive portion (see annotated Fig. 8 above) of the second conductive region (#8), and the third power chip (#15-18, #19-21) is connected to the second conductive branch (#5) of the fourth conductive region (#4).
Note, see 112(b) rejection of claim 9 above.
Regarding Claim 10, Bergmann in view of Murata discloses: The semiconductor power module according to claim 9,
Bergmann further discloses:
wherein the plurality of the first conductive branches (#4’, #4’’) and the plurality of the second conductive branches (#5, #6) are arranged alternately along the second direction (x-direction), and the first conductive branch (#4’) and the second conductive branch (#4’) that are adjacent to each other are connected through the third power chip (#15-18, #19-21).
Regarding Claim 11, Bergmann in view of Murata discloses: The semiconductor power module according to claim 9,
Bergmann further discloses:
wherein the first conductive branch (#4’) and the second conductive branch (#5) that are adjacent to each other are connected by a plurality of third power chips (#15-18 and #19-21) that are spaced apart along the first direction (y-direction), the third power chips (#15-18 and #19-21) located on two outermost sides in the second direction (x-direction) are same in quantity.
Regarding Claim 12, Bergmann in view of Murata discloses: The semiconductor power module according to claim 2,
Bergmann further discloses:
wherein the first conductive region (#7) has a first direct current connection point (see annotated Fig. 8 above) for receiving the direct current signal, the second conductive region (#8) has a second direct current connection point (see annotated Fig. 8 above) for receiving the direct current signal, the third conductive region (#4) has a third direct current connection point (see annotated Fig. 8 above) for receiving the direct current signal, and the fourth conductive region (#5, #6) has an alternating current connection point (see annotated Fig. 8 above);
wherein the first direct current connection point (see annotated Fig. 8 above), the second direct current connection point (see annotated Fig. 8 above), and the third direct current connection point (see annotated Fig. 8 above) are disposed on one side of the substrate (top side of #2) in the first direction (y-direction) and are arranged in the second direction (x-direction), the third direct current connection point (see annotated Fig. 8 above) is disposed between the first direct current connection point (see annotated Fig. 8 above) and the second direct current connection point (see annotated Fig. 8 above), a polarity of the direct current signal connected to the first direct current connection point ([0050]: “In FIG. 8 the AC terminal 55 is at one end of the substrate 2, and the positive 57 and negative 56 terminals are at the opposite end.”) is the same as a polarity of the direct current signal connected to the second direct current connection point ([0050]: “positive 57 and negative 56 terminals…”), a polarity of the direct current signal connected to the third direct current connection point (see annotated Fig. 8 above) is opposite to a polarity of the direct current signal connected to the first direct current connection point ([0050]: “In FIG. 8 the AC terminal 55 is at one end of the substrate 2, and the positive 57 and negative 56 terminals are at the opposite end.”), and the alternating current connection point ([0050]: “In FIG. 8 the AC terminal 55 is at one end of the substrate 2, and the positive 57 and negative 56 terminals are at the opposite end.”) is located on the other side of the substrate (#2) in the first direction (y-direction).
Regarding Claim 13, Bergmann in view of Murata discloses: The semiconductor power module according to claim 12,
Bergmann further discloses:
the first power chip (#11-14) is provided in the first conductive region (#7) and is electrically connected to the fourth conductive region (#5, #6), the second power chip (#23-26) is provided in the second conductive region (#8) and is electrically connected to the fourth conductive region (#5, #6), and the third power chip (#15-18, #19-21) is provided in the fourth conductive region (#5, #6) and is electrically connected to the third conductive region (#4).
Bergmann does not explicitly disclose:
wherein the first direct current connection point and the second direct current connection point are anodic direct current connection points and the third direct current connection point is a cathode direct current connection point; and
However, in analogous art, Murata teaches:
wherein the first direct current connection point and the second direct current connection point are anodic direct current connection points and the third direct current connection point is a cathode direct current connection point (Fig. 7, [0063]-[0073]);
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Murata to the device disclosed by Bergmann and form the first and second direct current connection points as anodic connection points and form the third direct current connection point as a cathodic connection point. Murata is silent as to the direction of current within the power device, and in analogous art, Murata discloses in Fig. 7 and paragraphs [0063]-[0073] the direction of current indicating the anodic/cathodic characteristic of the terminals and their respective connection points. Further, paragraph [0071] discloses “The positional relationship between the positive electrode terminal 17 and the negative electrode terminal 18 may be reversed from the one described above.” Therefore, the anodic/cathodic relationship may be reversed depending on the use case of the power device in real world application.
Regarding Claim 14, Bergmann in view of Murata discloses: The semiconductor power module according to claim 12,
Bergmann further discloses:
the first power chip (#11-14) is provided in the fourth conductive region (#5, #6) and is electrically connected to the first conductive region (#7), the second power chip (#23-26) is provided in the fourth conductive region (#5, #6) and is electrically connected to the second conductive region (#8), and the third power chip (#15-18, #19-21) is provided in the third conductive region (#4) and is electrically connected to the fourth conductive region (#5, #6).
Bergmann does not explicitly disclose:
wherein the first direct current connection point and the second direct current connection point are cathodic direct current connection points and the third direct current connection point is an anodic direct current connection point; and
However, in analogous art, Murata teaches:
wherein the first direct current connection point and the second direct current connection point are cathodic direct current connection points and the third direct current connection point is an anodic direct current connection point; and
(Fig. 7, [0063]-[0073]);
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Murata to the device disclosed by Bergmann and form the first and second direct current connection points as anodic connection points and form the third direct current connection point as a cathodic connection point. Murata is silent as to the direction of current within the power device, and in analogous art, Murata discloses in Fig. 7 and paragraphs [0063]-[0073] the direction of current indicating the anodic/cathodic characteristic of the terminals and their respective connection points. Further, paragraph [0071] discloses “The positional relationship between the positive electrode terminal 17 and the negative electrode terminal 18 may be reversed from the one described above.” Therefore, the anodic/cathodic relationship may be reversed depending on the use case of the power device in real world application.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0056722 A1 Bergmann et al in view of US 2020/0053900 A1 Feurtado et al (herein “Feurtado”).
Regarding Claim 19, Bergmann discloses:
A motor controller (#1, see generally the embodiment shown in Fig. 8 showing power module and various conductive regions), comprising:
a semiconductor power module (), the semiconductor power module comprises:
a substrate (#2, [0040]) having a first direction (#9, y-direction) and a second direction (#10, x-direction) that are orthogonal to each other;
a first conductive region (#7, see annotated Fig. 8 below),
a second conductive region (#8, see annotated Fig. 8 below),
a third conductive region (#4: 4’ and 4’’, [0048], see annotated Fig. 8 below), and
a fourth conductive region (#5 and #6, see annotated Fig. 8 below) that are disposed on the substrate (#2) and that are spaced apart from each other,
wherein the first conductive region (#7) and the second conductive region (#8) extend along the first direction (y-direction) of the substrate (#2) and are arranged along the second direction (x-direction) of the substrate (#2), the third conductive region (#4) and the fourth conductive region (#6) are located between the first conductive region (#7) and the second conductive region (#8) and are arranged along the first direction (y-direction), the first conductive region (#7), the second conductive region (#8) and the third conductive region (#4) are configured to transmit a direct current signal ([0003], [0024], [0049], [0052]), and the fourth conductive region (#5, #6) is configured to transmit an alternating current signal ([0003], [0024], [0049], [0052]); and
at least one first power chip (#11-14), at least one second power chip (#23-26), and at least one third power chip (#15-18 and #19-21), the first power chip (#11-14) is electrically connected to each of the first conductive region (#7) and the fourth conductive region (#5, #6), the second power chip (#23-26) is electrically connected to each of the second conductive region (#8) and the fourth conductive region (#4), and the third power chip (#15-18 and #19-21) is electrically connected to each of the fourth conductive region (#5, #6) and the third conductive region (#4).
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Bergmann Fig. 8 – Annotated by Examiner
Bergmann does not explicitly disclose:
a heat-dissipating base plate and a cooling liquid channel, the heat-dissipating base plate mounted to the cooling liquid channel, wherein the semiconductor power module is disposed on the heat-dissipating base plate
However, in analogous art, Feurtado teaches:
a heat-dissipating base plate and a cooling liquid channel, the heat-dissipating base plate mounted to the cooling liquid channel, wherein the semiconductor power module is disposed on the heat-dissipating base plate (see paragraph [0186] The FIG. 20 implementation may further include a cold plate 902. The cold plate 902 may be high performance liquid cold plate, heat sink, or the like, serving to transfer waste heat away from the power modules 100 to another source (liquid, air, etc.).).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Feurtado to the device disclosed by Bergmann and include a heat dissipating element comprising a heat sink and a cooling liquid element. Bergmann is silent as to the specific implementation of the heat dissipating element, and doing so would be an obvious modification to form a functional device to adequately and efficiently dissipate heat from the power module.
Regarding Claim 19, Bergmann in view of Feurtado discloses: the motor controller according to claim 19.
Bergmann further discloses:
A vehicle comprising a motor; and the motor controller according to claim 19 (see above) vehicle comprising a motor; and the motor controller according to wherein the motor controller is connected to the motor (see paragraph [0003] Semiconductor power modules are widely used in industry. For example, such a power module may be used for the controlled switching of high currents and can be used in power converters (such as inverters) to convert DC to AC or vice versa, or for converting between different voltages or frequencies of AC. Such inverters are used in motor controllers or interfaces between power generation or storage, or a power distribution grid. In addition, power modules are being increasingly utilized in vehicles, in particular electrical or hybrid vehicles, where the conversion or control of electrical power is important. In such an application, there are very great constraints on size, weight and efficiency.).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andrew V. Prostor whose telephone number is (571) 272-2686. The examiner can normally be reached M-F 8:00a-4:30p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ANDREW VICTOR PROSTOR/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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