DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 06/09/2026. Claims 1-20 are pending for this examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed on 06/07/2024.
Oath/Declaration
The oath or declaration filed on 05/12/21024 is acceptable.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/19/2025 and 05/12/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Election/Restrictions
Applicant’s election, without traverse Species I, directed to an embodiment as depicted in FIGS. 1, with claims 1-3, 5-7 and 17-20, in the “Response to Election / Restriction Filed” filed on 06/09/2026 is acknowledged.
However, the features of claim 18 “a first small signal conductive region provided in the substrate; and a first small signal input substrate provided in the second conductive region, wherein the first small signal input substrate is connected to each of the first small signal conductive region and the first power chip to transmit a gate signal to the first power chip” does not read on elected species I (Fig 1), and it appears read on non-elected embodiment Figure 8. Therefore, claim 18 is withdrawn.
This office action considers claims 1-20 are thus pending for prosecution and claims 4, 8-16 and 18 are withdrawn.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation “a fifth conductive region and a sixth conductive region that are respectively connected to both ends of the third conductive region, the fifth conductive region and the sixth conductive region are respectively located on both sides of the first conductive region in the second direction and on both sides of the second conductive region in the second direction, and the fifth conductive region and the sixth conductive region respectively spaced apart from the first conductive region and the second conductive region”, in claim 3, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 17 is objected to because of the following informalities:
Claim 17 recites the limitation “a polarity of the direct current signal connected to the second direct current connection point is the same as a polarity of the direct current signal connected to the third direct current connection point” in line 2 and lacks proper antecedent basis. For the purpose of examination, Examiner interpreted, “a polarity of the direct current signal connected to the second direct current connection point is same as a polarity of the direct current signal connected to the third direct current connection point”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding Claim 3, The instant claims recite limitation “wherein the third conductive region configured to receive the direct current signal via the fifth conductive region and the sixth conductive region” is not clear because, third conductive region configured to receive the direct current signal via the fifth conductive region and the sixth conductive region is not defined. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Regarding Claim 6, The instant claims recite limitation “wherein a plurality of first power chips are comprised, the plurality of the first power chips are arranged along the second direction, and two first power chips that are disposed adjacent to each other are staggered in the first direction; and a plurality of second power chips are comprised, the plurality of the second power chips are arranged along the second direction, and two second power chips that are disposed adjacent to each other are staggered in the first direction” is not clear because claim 1 recites “at least one first power chip and at least one second power chip”. It is not clear plurality of first power chips and two first power chips are different then at least at least first power chip and at least one second power chip or they are same chip. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 5 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Iguchi (US 2021/0351161 A1; hereafter Iguchi).
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Regarding claim 1. Iguchi discloses a semiconductor power module (Fig 1), comprising:
a substrate (Fig 1, substrate 30, Para [ 0023]) having a first direction and a second direction that are orthogonal to each other (Fig 1, substrate 30, Para [ 0023]);
a first conductive region ( Fig 1, positive terminal P, construed as first conductive region, Para [ 0057-0058]), a second conductive region ( source electrode 11a, construed as second conductive region, Para [ 0037]), a third conductive region (source electrode 12a, construed as third conductive region, Para [ 0024]), and a fourth conductive ( AC output terminal, construed as fourth conductive region, Para [ 0064]) disposed on the substrate (Fig 1, substrate 30, Para [ 0023]) that are spaced apart from each other, and that are arranged in sequence along the first direction of the substrate (Fig 1, substrate 30, Para [ 0023]), wherein each of the first conductive region ( positive terminal P, Para [ 0064]), the second conductive region ( source electrode 11a), the third conductive region (source electrode 12a), and the fourth conductive region ( AC output terminal, Para [ 0064]) extends along the second direction of the substrate (Fig 1, substrate 30, Para [ 0023]), the first conductive region ( positive terminal P, Para [ 0064]) and the third conductive region (source electrode 12a) are configured to transmit a direct current signal ( signal transmit form positive terminal to source electrode 11a), and the fourth conductive region ( AC output terminal, Para [ 0064]) is configured to transmit an alternating current signal ( AC output terminal , Para [ 0064]); and
at least one first power chip (third semiconductor chip 21, Para [ 0025]) and at least one second power chip ( fourth semiconductor chip 22, Para [ 0025]), the first power chip (third semiconductor chip 21) is electrically connected to each of the first conductive region ( positive terminal P, Para [ 0064]) and the second conductive region ( source electrode 11a), the second power chip ( fourth semiconductor chip 22) is electrically connected to each of the second conductive region ( source electrode 11a), the third conductive region (source electrode 12a) and the fourth conductive region ( AC output terminal , Para [ 0064]).
Examiner like to note that, positive terminal P can have DC current signal. It is evidence by Gloes et al US 2019/0199193 A1, Para [ 0046]).
Regarding claim 2. Iguchi discloses the semiconductor power module according to claim 1, Iguchi further discloses wherein the first conductive region (Fig 1, positive terminal P, Para [ 0057-0058]) and the third conductive region (source electrode 12a) are configured to receive the direct current signal (based on the positive signal received from terminal P, Para [ 0064]), and the fourth conductive region is configured to output the alternating current signal (AC output terminal, Para [ 0064]).
Regarding claim 5. Iguchi discloses the semiconductor power module according to claim 1, Iguchi further discloses wherein the first power chip (third semiconductor chip 21, Para [ 0025]) and the second power chip (fourth semiconductor chip 22, Para [ 0025]) are arranged along the first direction (Fig 1, Para [ 0021-0026]).
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Iguchi (US 2021/0351161 A1; hereafter Iguchi) in view of Esler et al (US 2022/0070996 A1; hereafter Esler).
Regarding claim 19. Iguchi discloses a motor controller comprising:
a heat-dissipating base plate (“a heat dissipation plate (not illustrated) is connected to a rear surface of the metal base 28 “, Para [ 0028]) and
a semiconductor power module (Fig 1) including:
a substrate (Fig 1, substrate 30, Para [ 0023]) having a first direction and a second direction that are orthogonal to each other (Fig 1, substrate 30, Para [ 0023]);
a first conductive region ( Fig 1, positive terminal P, construed as first conductive region, Para [ 0057-0058]), a second conductive region ( source electrode 11a, construed as second conductive region, Para [ 0037]), a third conductive region (source electrode 12a, construed as third conductive region, Para [ 0024]), and a fourth conductive ( AC output terminal, construed as fourth conductive region, Para [ 0064]) disposed on the substrate (Fig 1, substrate 30, Para [ 0023]) that are spaced apart from each other, and that are arranged in sequence along the first direction of the substrate (Fig 1, substrate 30, Para [ 0023]), wherein each of the first conductive region ( positive terminal P), the second conductive region ( source electrode 11a), the third conductive region (source electrode 12a), and the fourth conductive region ( AC output terminal, Para [ 0064]) extends along the second direction of the substrate (Fig 1, substrate 30, Para [ 0023]), the first conductive region ( positive terminal P, Para [ 0064]) and the third conductive region (source electrode 12a) are configured to transmit a direct current signal ( signal transmit form positive terminal to source electrode 11a), and the fourth conductive region ( AC output terminal, Para [ 0064]) is configured to transmit an alternating current signal ( AC output terminal , Para [ 0064]); and
at least one first power chip (third semiconductor chip 21, Para [ 0025]) and at least one second power chip ( fourth semiconductor chip 22, Para [ 0025]), the first power chip (third semiconductor chip 21) is electrically connected to each of the first conductive region ( positive terminal P, Para [ 0064]) and the second conductive region ( source electrode 11a), the second power chip ( fourth semiconductor chip 22) is electrically connected to each of the second conductive region ( source electrode 11a), the third conductive region (source electrode 12a) and the fourth conductive region ( AC output terminal , Para [ 0064]);
Examiner like to note that, positive terminal P can have DC current signal. It is evidence by Gloes et al US 2019/0199193 A1, Para [ 0046]).
But Iguchi does not disclose explicitly a cooling liquid channel, the heat-dissipating base plate mounted to the cooling liquid channel; and wherein the semiconductor power module is disposed on the heat-dissipating base plate.
In a similar field of endeavor, Esler discloses a cooling liquid channel ( Fig 1, heat sink 271, Para [ 0028]), the heat-dissipating base plate (conductive plate 281, Para [ 0026]) mounted to the cooling liquid channel ( heat sink 271, Para [ 0028]); and wherein the semiconductor power module ( power overlay POL module 200, Para [ 0020]) is disposed on the heat-dissipating base plate (conductive plate 281, Para [ 0026]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Iguchi in light of Esler teaching “a cooling liquid channel ( Fig 1, heat sink 271, Para [ 0028]), the heat-dissipating base plate (conductive plate 281, Para [ 0026]) mounted to the cooling liquid channel ( heat sink 271, Para [ 0028]); and wherein the semiconductor power module ( power overlay POL module 200, Para [ 0020]) is disposed on the heat-dissipating base plate (conductive plate 281, Para [ 0026])” for further advantage such as to improve heat dissipation in the power module.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Iguchi (US 2021/0351161 A1; hereafter Iguchi) in view of Esler et al (US 2022/0070996 A1; hereafter Esler) as applied claims above and further in view of ZENG et al (US 2021/0261074 A1; hereafter ZENG).
Regarding claim 20. Iguchi in light of Esler discloses according to claim 19, but fails to discloses a vehicle comprising:
a motor; and the motor controller according to claim 19, wherein the motor controller is connected to the motor.
In a similar field of endeavor, ZENG discloses a motor (claim 1); and the motor controller (claim 1), wherein the motor controller is connected to the motor (Para [ 0080-0084]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Iguchi and Esler in light of ZENG teaching “a motor (claim 1); and the motor controller (claim 1), wherein the motor controller is connected to the motor (Para [ 0080-0084])” for further advantage such as integrated controller that ensures optimized use of space, reduced cost, and convenient detection of aging modules.
Alternate Rejection:
Claims 1 and 7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Iguchi (US 2021/0351161 A1; hereafter Iguchi).
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Regarding claim 1. Iguchi discloses a semiconductor power module (Fig 5), comprising:
a substrate (Fig 5, substrate 30, Para [ 0023]) having a first direction and a second direction that are orthogonal to each other (Fig 1, substrate 30, Para [ 0023]);
a first conductive region ( Fig 5, positive terminal P, construed as first conductive region, Para [ 0057-0058]), a second conductive region ( Fig 5, first metal layer 31, Para [ 0023]), a third conductive region (Fig 5, second metal layer 32, Para [ 0023]), and a fourth conductive (Fig 5, AC output terminal, construed as fourth conductive region, Para [ 0064, 0081]) disposed on the substrate (Fig 5, substrate 30, Para [ 0023]) that are spaced apart from each other (Fig 5), and that are arranged in sequence along the first direction of the substrate (Fig 5, substrate 30, Para [ 0023]), wherein each of the first conductive region ( Fig 5, positive terminal P, construed as first conductive region, Para [ 0057-0058]), the second conductive region (Fig 5, first metal layer 31, Para [ 0023]), the third conductive region (Fig 5, second metal layer 32, Para [ 0023]), and the fourth conductive region (Fig 5, AC output terminal, Para [ 0064]) extends along the second direction of the substrate (Fig 5, substrate 30), the first conductive region ( positive terminal P) and the third conductive region (Fig 5, second metal layer 32, Para [ 0023]) are configured to transmit a direct current signal (Fig 5, signal transmit form positive terminal), and the fourth conductive region ( Fig 5, AC output terminal, Para [ 0064]) is configured to transmit an alternating current signal ( AC output terminal , Para [ 0064]); and
at least one first power chip (semiconductor chip 11, Para [ 0025]) and at least one second power chip (semiconductor chip 21, Para [ 0025]), the first power chip (semiconductor chip 11, Para [ 0025]) is electrically connected to each of the first conductive region ( positive terminal P) and the second conductive region ( first metal layer 31, Para [ 0023]), the second power chip (semiconductor chip 21) is electrically connected to each of the second conductive region ( first metal layer 31, Para [ 0023]), the third conductive region (semiconductor chip 21, Para [ 0025]) and the fourth conductive region ( AC output terminal, Para [ 0064]).
Examiner like to note that, positive terminal P can have DC current signal. It is evidence by Gloes et al US 2019/0199193 A1, Para [ 0046]).
Regarding claim 7. Iguchi discloses the semiconductor power module according to claim 1, Iguchi discloses wherein the first power chip (semiconductor chip 11, Para [ 0025]) is provided in the second conductive region (first metal layer 31, Para [ 0023]), and the second power chip (semiconductor chip 21) is provided in the third conductive region (Fig 5, second metal layer 32, Para [ 0023]).
Allowable Subject Matter
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 17. wherein the first conductive region has a first direct current connection point for receiving the direct current signal on a side of the first conductive region that faces away from the second conductive region, the fifth conductive region has a second direct current connection point for receiving the direct current signal on an end of the fifth conductive region that is further away from the third conductive region, the sixth conductive region has a third direct current connection point for receiving the direct current signal on an end of the sixth conductive region that that is further away from the third conductive region, and the fourth conductive region has an alternating current connection point on a side of the fourth conductive region that faces away from the third conductive region; and wherein the first direct current connection point, the second direct current connection point, and the third direct current connection point are disposed on one side of the substrate in the first direction and are arranged in the second direction, the first direct current connection point is disposed between the second direct current connection point and the third direct current connection point, a polarity of the direct current signal connected to the second direct current connection point is the same as a polarity of the direct current signal connected to the third direct current connection point, a polarity of the direct current signal connected to the third direct current connection point is opposite to a polarity of the direct current signal connected to the first direct current connection point, and the alternating current connection point is located on another side of the substrate in the first direction.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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