DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention Group I (currently Claims 1-9) in the reply filed on 9/3/2026 is acknowledged. Applicant has cancelled non-elected Claims 10-19 (corresponding to invention Group II).
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 5/13/2024, 11/6/2024, and 9/24/2025. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lichtenwalner et al (US 9,887,287 B1, hereafter Lichtenwalner).
Re Claim 1, Lichtenwalner discloses a semiconductor device (FIG. 4B; column 11, line 56 to column 15, line 51), comprising:
an epitaxial layer (430; column 12, lines 28-33) having a first conductive type (n-type; column 12, lines 28-33);
a gate structure (482, 484; column 14, lines 34-37) disposed in the epitaxial layer (430; column 14, lines 34-37);
a well (440, 444; column 13, lines 53-57) disposed in the epitaxial layer (430; column 13, lines 53-57) and having a second conductive type (p-type; column 13, lines 40-44) different from the first conductive type (n-type; column 13, lines 40-44), wherein the well (440, 444) extends from a sidewall of the gate structure (482, 484, right sidewall) to a bottom surface of the gate structure (482, 484; column 13, lines 53-57); and
a source electrode (490; column 14, lines 44-46) disposed above the epitaxial layer (430; column 14, lines 44-46) and electrically connected to the well (440, 444; column 14, lines 44-46).
Re Claim 2, Lichtenwalner discloses the semiconductor device according to Claim 1, while further disclosing wherein a junction between the sidewall and the bottom surface of the gate structure (482, 484) is completely covered by the well (440, 444; column 13, lines 53-57).
Re Claim 3, Lichtenwalner discloses the semiconductor device according to Claim 1, while further disclosing wherein a depth of a bottom surface of the well (440, 444) is greater than about 1 micron (column 14, lines 63-67).
Re Claim 4, Lichtenwalner discloses the semiconductor device according to Claim 1, while further disclosing wherein the well (440, 444) has a first portion (P1, see FIG. Z1 below) and a second portion (P2, see FIG. Z1 below; column 13, lines 53-57), wherein the first portion (P1) surrounds the sidewall of the gate structure (482, 484, right sidewall, at least partially surrounding, in part due to curve of bottom right corner of 482 in FIG. 4B; column 13, lines 53-57) and is in contact with the sidewall (482, 484, right sidewall; column 13, lines 53-57), and the second portion (P2) is disposed below the gate structure (482, 484) and is in contact with the bottom surface of the gate structure (482, 484; column 13, lines 53-57).
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FIG. Z1: Annotated version of FIG. 4B of Lichtenwalner
Re Claim 5, Lichtenwalner discloses the semiconductor device according to Claim 4, while further disclosing wherein the second portion (P2) has an opening (“the opening”, see FIG. Z1; column 13, lines 53-57) and the epitaxial layer (430) is in contact with the bottom surface of the gate structure (482, 484) through the opening (“the opening”; column 13, lines 53-57).
Re Claim 6, Lichtenwalner discloses the semiconductor device according to Claim 4, while further disclosing wherein a depth of a top surface of the first portion (P1, topmost surface has depth of 0; column 13, lines 53-57) is less than a depth of a top surface of the second portion (P2, topmost surface depth greater than 0; column 13, lines 53-57).
Re Claim 7, Lichtenwalner discloses the semiconductor device according to Claim 4, while further disclosing wherein a doping concentration of the first portion (P1) is substantially equal to a doping concentration of the second portion (P2; column 14, lines 10-33, at least at their intersection).
Claims 1 and 8-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Konstantinov (US 2017/0012119 A1).
Re Claim 1, Konstantinov discloses a semiconductor device (FIG. 2; [0042]-[0046]), comprising:
an epitaxial layer (215; [0042]) having a first conductive type (n-type; [0042]);
a gate structure (240, 245; [0042]) disposed in the epitaxial layer (215; [0042]);
a well (220; [0042]) disposed in the epitaxial layer (215; [0042]) and having a second conductive type (p-type; [0042]) different from the first conductive type (n-type; [0042]), wherein the well (220) extends from a sidewall of the gate structure (240, 245) to a bottom surface of the gate structure (240, 245; [0042]); and
a source electrode (230; [0042]) disposed above the epitaxial layer (215; [0042]) and electrically connected to the well (220; [0042]).
Re Claim 8, Konstantinov discloses the semiconductor device according to Claim 1, while further disclosing the device comprises a heavily doped region (223; [0043]), wherein the heavily doped region (223) is disposed between the well (220) and the source electrode (230; [0043]), the heavily doped region (223) has the second conductive type (p-type; [0043]), and the heavily doped region (223) has a doping concentration greater than a doping concentration of the well (220; [0043]).
Re Claim 9, Konstantinov discloses the semiconductor device according to Claim 8, while further disclosing the device comprises a source region (235; [0042]) having the first conductive type (n-type; [0042]) and disposed between the gate structure (240, 245) and the heavily doped region (223; [0043]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST.
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/COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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