DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 05/13/2024, have being considered by the examiner.
Claim Objections
Claim 7 is objected to because of the following informalities:
In Claim 7, Line 6-7, the term “increases, and and” should be changed to, “increases, and for typographical issues. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-3, 10, and 18, are rejected under 35 U.S.C. 102(a)(1) / (a)(2) as being anticipated by Chung et al. (US 20230411431 A1), hereinafter referenced as Chung.
Regarding claim 1, Chung teaches a semiconductor device (Fig. 16, #1600 called an image sensor. Paragraph [0099]) comprising:
a substrate (Fig. 16, #1602b called a third semiconductor substrate. Paragraph [0100]);
a first transistor on the substrate (Fig. 16, #804 called a third transistor. Paragraph [0103]-Chung discloses the third transistors 804 (only one of which is shown) are on a frontside of the third semiconductor substrate 1602.);
a first contact on a source/drain pattern (Fig. 16, #1610 called an individual pairs of third source/drain regions wherein the first contact is the part connecting to third source/drain regions #1610. Paragraph [0103]) of the first transistor (Fig. 16, illustrates the first contact on the source/drain pattern #1610 of the first transistor #804 in the 1614 region leading up wards. Paragraph [0106]);
a second transistor on the substrate (Fig. 16 and 21, #804 called a third transistor. Paragraph [0103]-Chung discloses the third transistors 804 (only one of which is shown) are on a frontside of the third semiconductor substrate 1602.);
a second contact on a gate electrode of the second transistor (Fig. 16, and 21, #1604 called third gate electrodes. Paragraph [0103]-Chung discloses the third transistors 804 (only one of which is shown) are on a frontside of the third semiconductor substrate 1602. Further, the third transistors 804 comprise individual third gate electrodes 1604, individual third gate dielectric layers 1606, individual third sidewall spacers 1608, and individual pairs of third source/drain regions 1610.);
a first connecting structure (Fig. 16, and 21, #1614 called third interconnect structure. Paragraph [0106]) that comprises at least one first wiring and at least one first via that are alternately stacked on the first contact (Fig. 16, illustrates first wiring #1434 and first via #1436. Paragraph [0106]-Chung discloses the third interconnect structure 1614 covers the third transistors 804 on a frontside of the third interconnect structure 1614. Further, the third interconnect structure 1614 is as the first and second interconnect structures 1430, 1432 are described. Hence, the third interconnect structure 1614 comprises a plurality of additional conductive wires 1434 and a plurality of additional conductive vias 1436 stacked in a corresponding interconnect dielectric layer 1438. These conductive wires and vias 1434, 1436 define conductive paths leading from the third transistors 804.);
a second connecting structure (Fig. 16, and 21, #1432 called the second interconnect structure. Paragraph [0106]) that comprises at least one second wiring and at least one second via that are alternately stacked on the second contact (Fig. 16, and 21, illustrates second wiring #1434 and at least one second via #1436 in the second interconnect structure #1432. Paragraph [0106]-Chung discloses Further, the third interconnect structure 1614 is as the first and second interconnect structures 1430, 1432 are described. Hence, the third interconnect structure 1614 comprises a plurality of additional conductive wires 1434 and a plurality of additional conductive vias 1436 stacked in a corresponding interconnect dielectric layer 1438. These conductive wires and vias 1434, 1436 define conductive paths leading from the third transistors 804.);
a first connecting via on the first connecting structure (Fig. 16, and 21, illustrates first connecting via #1624 called a bond vias is located in the bond dielectric layer #1620 under the additional bond interface #1618 on the third interconnect structure #1614. Paragraph [0106 and 0108]);
a second connecting via on the second connecting structure (Fig. 16, and 21, illustrates second connecting via #1624 called a bond vias is located in the bond dielectric layer #1620 over the additional bond interface #1618 on the second interconnect structures #1432. Paragraph [0092 and 0108]); and
a connecting wiring on the first connecting via and the second connecting via (Fig. 16, and 21, illustrates connecting wiring #1622 on the first connecting via #1624 called a bond vias is located in the bond dielectric layer #1620 under the additional bond interface #1618 on the third interconnect structure #1614 and the second connecting via #1624 called a bond vias is located in the bond dielectric layer #1620 over the additional bond interface #1618 on the second interconnect structures #1432. Paragraph [0106 and 0108]. Please see the annotated figure 16 below.).
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Regarding claim 2, Chung teaches the semiconductor device of claim 1, Chung further teaches wherein the first connecting structure and the second connecting structure are electrically connected by the connecting wiring, the first connecting via, and the second connecting via (Fig. 16, and 21, illustrates connecting wiring #1622 on the first connecting via #1624 called a bond vias is located in the bond dielectric layer #1620 under the additional bond interface #1618 on the third interconnect structure #1614 and the second connecting via #1624 called a bond vias is located in the bond dielectric layer #1620 over the additional bond interface #1618 on the second interconnect structures #1432. Paragraph [0106 and 0108]-Chung discloses the additional bond structure 1616 comprise additional bond dielectric layers 1620 individual to the second and third IC chips 104b, 104c and directly contacting and bonded together at the additional bond interface 1618. Further, the additional bond structure 1616 comprise additional bond pads 1622 individual to the second and third IC chips 104b, 104c and directly contacting and bonded together at the additional bond interface 1618. The additional bond pads 1622 are inset respectively into the additional bond dielectric layers 1620 and are electrically coupled respectively to the third interconnect structure 1614 and a TSV 1626 by additional bond vias 1624 respectively in the additional bond dielectric layers 1620. Please see the annotated figure 16 below.).
Regarding claim 3, Chung teaches the semiconductor device of claim 1, Chung further teaches wherein each of the at least one second via is respectively on each of the at least one second via (Fig. 16, and 21, illustrates the at least one second via #1436 in the second interconnect #1432 is respectively on each of the at least one second via. Paragraph [0106]-Chung discloses Further, the third interconnect structure 1614 is as the first and second interconnect structures 1430, 1432 are described. Hence, the third interconnect structure 1614 comprises a plurality of additional conductive wires 1434 and a plurality of additional conductive vias 1436 stacked in a corresponding interconnect dielectric layer 1438. These conductive wires and vias 1434, 1436 define conductive paths leading from the third transistors 804.).
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Regarding claim 10, Chung teaches the semiconductor device of claim 1, Chung further teaches wherein: the at least one first via comprises a third via (Fig. 16 and 21. Paragraph [0106]-Chung discloses the third interconnect structure 1614 comprises a plurality of additional conductive wires 1434 and a plurality of additional conductive vias 1436 stacked in a corresponding interconnect dielectric layer 1438. These conductive wires and vias 1434, 1436 define conductive paths leading from the third transistors 804.), the at least one second via comprises a fourth via (Fig. 16 and 21. Paragraph [0092]-Chung discloses first and second interconnect structures 1430, 1432 comprise a plurality of conductive wires 1434 and a plurality of conductive vias 1436 stacked in corresponding interconnect dielectric layers 1438.),
the third via and the fourth via are on a same via layer (Fig. 16 and 21, illustrates the third via and the fourth via are on a same via layer #1438. Paragraph [0092]), and
a length of the fourth via is greater than a length of the third via (Fig. 21, illustrates the length of the fourth via is greater than a length of the third via. Paragraph [0106]. Please see annotated diagram of Chung Fig. 21 below for details.).
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Regarding claim 18, Chung teaches a semiconductor device (Fig. 16, #1600 called an image sensor. Paragraph [0099]) comprising:
a first cell (Fig. 16, and 21, #104c called a third IC chips. Paragraph [0076]);
a first connecting via on the first cell (Fig. 16, and 21, illustrates first connecting via #1624 called a bond vias is located in the bond dielectric layer #1620 under the additional bond interface #1618 on the third interconnect structure #1614 on the first cell. Paragraph [0106 and 0108]);
a second cell (Fig. 16, and 21, #104b called a second IC chips. Paragraph [0078]);
a second connecting via on the second cell (Fig. 16, and 21, illustrates second connecting via #1624 called a bond vias is located in the bond dielectric layer #1620 over the additional bond interface #1618 on the second interconnect structures #1432 on the second cell. Paragraph [0092 and 0108]); and
a connecting wiring that is on and electrically connects the first connecting via and the second connecting via (Fig. 16, and 21, illustrates connecting wiring #1622 on the first connecting via #1624 called a bond vias is located in the bond dielectric layer #1620 under the additional bond interface #1618 on the third interconnect structure #1614 and the second connecting via #1624 called a bond vias is located in the bond dielectric layer #1620 over the additional bond interface #1618 on the second interconnect structures #1432. Paragraph [0106 and 0108]. Please see the annotated figure 16 below.),
wherein the first cell (Fig. 16, and 21, #104c called a third IC chips. Paragraph [0076]) comprises:
a first transistor (Fig. 16, #804n/804 called a third transistor. Paragraph [0103]-Chung discloses the third transistors 804 (only one of which is shown) are on a frontside of the third semiconductor substrate 1602.),
a first contact on a source/drain pattern of the first transistor (Fig. 16, #1610 called an individual pairs of third source/drain regions wherein the first contact is the part connecting to third source/drain regions #1610. Paragraph [0103]) of the first transistor (Fig. 16, illustrates the first contact on the source/drain pattern #1610 of the first transistor #804 in the 1614 region leading up wards. Paragraph [0106]),
and a first connecting structure (Fig. 16, and 21, illustrates the bottom half of #1616 called additional bond structure wherein is the first connecting structure. Paragraph [0107]) that comprises at least one first wiring and at least one first via (Fig. 16, illustrates first wiring #1622 and first via #1624. Paragraph [0108]-Chung discloses the additional bond pads 1622 are inset respectively into the additional bond dielectric layers 1620 and are electrically coupled respectively to the third interconnect structure 1614 and a TSV 1626 by additional bond vias 1624 respectively in the additional bond dielectric layers 1620.),
wherein the first connecting structure electrically connects the first contact and the first connecting via (Fig. 16, and 21, illustrates the at least one first wiring #1622 and the at least one first via #1624 are connected. Paragraph [0108]-Chung discloses the additional bond pads 1622 are inset respectively into the additional bond dielectric layers 1620 and are electrically coupled respectively to the third interconnect structure 1614 and a TSV 1626 by additional bond vias 1624 respectively in the additional bond dielectric layers 1620.),
wherein the second cell (Fig. 16, and 21, #104b called a second IC chips. Paragraph [0078]) comprises:
a second transistor (Fig. 16, #112/116 called a second transistor. Paragraph [0092]-Chung discloses via layers and wire layers at the second interconnect structure 1432 are alternatingly stacked to define conductive paths leading from the second transistors 112.),
a second contact on a gate electrode of the second transistor (Fig. 16, and 21, illustrates a second contact on a gate electrode #1420 of the second transistor #112/116. Paragraph [0089]-Chung discloses the second transistors 112 (only one of which is shown) are on a frontside of the second semiconductor substrate 1404. Further, the second transistors 112 comprise individual second gate electrodes 1420, individual second gate dielectric layers 1422, individual second sidewall spacers 1424, and individual pairs of second source/drain regions 1426.),
and a second connecting structure (Fig. 16, and 21, illustrates the top half of #1616 called additional bond dielectric layer #1620 wherein is the second connecting structure. Paragraph [0108]) that comprises at least one second wiring and at least one second via (Fig. 16, illustrates second wiring #1622 and second via #1624 in the top region additional bond dielectric layers #1620. Paragraph [0108]-Chung discloses the additional bond pads 1622 are inset respectively into the additional bond dielectric layers 1620 and are electrically coupled respectively to the third interconnect structure 1614 and a TSV 1626 by additional bond vias 1624 respectively in the additional bond dielectric layers 1620.),
wherein the second connecting structure (Fig. 16, and 21, illustrates the top half of #1616 called additional bond dielectric layer #1620 wherein is the second connecting structure. Paragraph [0108]) electrically connects the second contact (Fig. 16, and 21, illustrates a second contact on a gate electrode #1420 of the second transistor #112/116. Paragraph [0089]) and the second connecting via (Fig. 16, and 21, illustrates the second contact on the transistor #112/116 gate #1420 is electrically connected to second connecting via #1624 called a bond vias is located in the bond dielectric layer #1620 over the additional bond interface #1618 on the second interconnect structures #1432 by the TSV #1626. Paragraph [0108]-Chung discloses the additional bond pads 1622 are inset respectively into the additional bond dielectric layers 1620 and are electrically coupled respectively to the third interconnect structure 1614 and a TSV 1626 by additional bond vias 1624 respectively in the additional bond dielectric layers 1620.).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 20, is rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (US 20230411431 A1), hereinafter referenced as Chung in view of LEE et al. (US 20230094686 A1), hereinafter referenced as LEE.
Regarding claim 20, Chung teaches the semiconductor device of claim 18, Chung further teaches wherein: the at least one first wiring comprises a third wiring that is electrically connected to the first connecting via (Fig. 16, and 21, illustrates first wiring #1622 and first via #1624 is connected to third wiring #1434 in 104b. Paragraph [0108]-Chung discloses the additional bond pads 1622 are inset respectively into the additional bond dielectric layers 1620 and are electrically coupled respectively to the third interconnect structure 1614 and a TSV 1626 by additional bond vias 1624 respectively in the additional bond dielectric layers 1620.),
the at least one second wiring comprises a fourth wiring that is electrically connected to the second connecting via (Fig. 16, and 21, illustrates the second contact on the transistor #112/116 gate #1420 is electrically connected to second connecting via #1624 called a bond vias is located in the bond dielectric layer #1620 over the additional bond interface #1618 on the second interconnect structures #1432 by the TSV #1626 in another column see Fig. 21 comprises a fourth wiring. Paragraph [0108]-Chung discloses the additional bond pads 1622 are inset respectively into the additional bond dielectric layers 1620 and are electrically coupled respectively to the third interconnect structure 1614 and a TSV 1626 by additional bond vias 1624 respectively in the additional bond dielectric layers 1620.),
Although, Chung teaches and the third wiring and the fourth wiring comprise a first material (Fig. 16 and 21. Paragraph [0106]-Chung discloses connect structure 1614 comprises a plurality of additional conductive wires 1434 and a plurality of additional conductive vias 1436 stacked in a corresponding interconnect dielectric layer 1438. These conductive wires and vias 1434, 1436 define conductive paths leading from the third transistors 804 (wherein the material is a conductive material a first material.).).
Chung fails to explicitly teach the first connecting via and the second connecting via comprise a second material.
However, LEE explicitly teaches the first connecting via and the second connecting via comprise a second material (Fig. 2. Paragraph [0035]-LEE discloses each of the first via barrier layer 49 and the first wiring barrier layer 59 may comprise one or more materials including, but not limited to, titanium (Ti), tantalum (Ta), cobalt (Co), TiN and/or TaN, but example embodiments thereof are not limited to these kinds of materials and these materials may be supplemented and/or replaced with other conductive materials. In an example, each of the first via gapfill pattern 51 and the first wiring gapfill pattern 61 may comprise one or more materials including, but not limited to, aluminum (Al), copper (Cu) and/or tungsten (W), but example embodiments thereof are not limited to these materials and may be supplemented and/or replaced with other conductive materials (wherein the connecting via comprise a second material.).).
Wherein having Chung`s semiconductor device wherein the first connecting via and the second connecting via comprise a second material.
The motivation behind the modification would have been to obtain an semiconductor device system that enhances a semiconductor device having a via and wiring, in which reliability may be improved, may obtain optimization and low manufacturing cost, since both Chung and LEE comprises of semiconductor device, materials and substrate with via and wiring, wherein Chung semiconductor device that a CMOS image sensors are increasingly favored due to low power consumption, small size, fast data processing, a direct output of data, and low manufacturing cost while LEE semiconductor device that use multiple materials may thereof are not limited to such material types and may be supplemented and/or replaced by other conductive materials. Please see Chung et al. (US 20230411431 A1), Paragraph [0002] and LEE et al. (US 20210043556 A1), Paragraph [0035 and 0120].
Allowable Subject Matter
Claims 4, 5, 7, 9, 11, and 19, along with dependent claims 6, 8, are therefrom objected to as being dependent upon rejected base claims, claims 1, and 18 but would be allowable if rewritten in independent form including all of the limitations of the base claims and any intervening claims once the claim objection is overcome.
Claim 12 an independent claim comprises of allowable subject matter, therefore claim 12 and its dependent claims 13-17 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, the prior arts fail to explicitly teach, a first set of widths from among the first width, the second width, and third width decreases as a respective first set of distances from among the first distance, the second distance, and the third distance increases, and a second set of widths from among the first width, the second width, and the third width increases as a respective second set of distances from among the first distance, the second distance, and the third distance increases.as claimed in claim 4.
Regarding claim 5, the prior arts fail to explicitly teach, a width of the third via increases as a distance between the third via and the substrate increases, a width of the fourth via increases as a distance between the fourth via and the substrate increases,
a width of the third wiring decreases as a distance between the third wiring and the substrate increases, and
a width of the fourth wiring decreases as a distance between the fourth wiring and the substrate increases.as claimed in claim 5.
Regarding claim 7, the prior arts fail to explicitly teach, a width of the third wiring decreases as a distance between the third wiring and the substrate increases, and and
a width of the fourth wiring decreases as a distance between the fourth wiring and the substrate increases as claimed in claim 7.
Regarding claim 9, the prior arts fail to explicitly teach, a width of the third via increases as a distance between the third via and the substrate increases, a width of the fourth via increases as a distance between the fourth via and the substrate increases,
a width of the third wiring increases as a distance between the third wiring and the substrate increases, and a width of the fourth wiring increases as a distance between the fourth wiring and the substrate increases as claimed in claim 9.
Regarding claim 11, the prior arts fail to explicitly teach, a width of the first connecting via increases as a distance between the first connecting via and the substrate increases, a width of the second connecting via increases as a distance between the second connecting via and the substrate increases, and a width of the connecting wiring increases as a distance between the connecting wiring and the substrate increases as claimed in claim 11.
Regarding claim 12, the prior arts fail to explicitly teach, a distance between a third wiring at an uppermost part of the at least one first wiring and a fourth wiring at an uppermost part of the at least one second wiring increases as a distance between the third wiring and the substrate increases or as a distance between the fourth wiring and the substrate increases as claimed in claim 12.
Regarding claim 19, the prior arts fail to explicitly teach, wherein a sum of an area of an upper side of the at least one second wiring and an area of the at least one second via is less than a sum of an area of an upper side of the at least one first wiring and an area of the at least one first via as claimed in claim 19.
.
Conclusion
Listed below are the prior arts made of record and not relied upon but are considered pertinent to applicant`s disclosure.
JIN et al. (US 20130334656 A1)- Provided are electrical connection structures and methods of fabricating the same. The structures may include a substrate including a bonding pad region provided with a bonding pad and a fuse region provided with a fuse, an insulating layer provided on the substrate and including a bonding pad opening exposing the bonding pad and a fuse opening exposing the fuse region, a connection terminal provided in the bonding pad region and electrically connected to the bonding pad, and a protection layer provided on the insulating layer including a first protection layer provided within the bonding pad region and a second protection layer in the fuse opening...... ...... Fig. 1. Abstract.
Sekar et al. (US 20120306082 A1)- A device, including: a first layer of first transistors, overlaid by at least one interconnection layer, wherein the interconnection layer includes metals such as copper or aluminum; a second layer including second transistors, the second layer overlaying the interconnection layer, wherein the second layer is less than about 0.4 micron thick; and a connection path connecting the second transistors to the interconnection layer, wherein the connection path includes at least one through-layer via, and the through-layer via includes material whose co-efficient of thermal expansion is within about 50 percent of the second layer coefficient of thermal expansion.......... ...... Fig. 1. Abstract.
KANG et al. (US 20210020497 A1)- A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal.............. Fig. 1-3. Abstract.
LEE (US 20220157849 A1)- Semiconductor memory device comprises a gate stacked structure; a channel layer passing through the gate stacked structure in a vertical direction; a memory layer disposed between the channel layer and the gate stacked structure; a dummy stacked structure extended toward the gate stacked structure.............. Fig. 1-3. Abstract.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHINEYERE D WILLS-BURNS whose telephone number is (571)272-9752. The examiner can normally be reached on Monday -Friday, 7:00 am - 5:00 pm.
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/CHINEYERE WILLS-BURNS/Supervisory Patent Examiner, Art Unit 2673
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