DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicant’s election of Species B and E, claims 1-14, 16, 19 and 20, in the reply filed on 14 July 2026 is acknowledged. Claims 15, 17, and 18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species, there being no allowable generic or linking claim. Applicant timely traversed the Election Requirement on the ground(s) that examination of all of the identified species and all of the pending claims would not result in a serious search and/or examination burden. This is not found persuasive for the reasons set forth in the Election Requirement. The requirement is still deemed proper and is therefore made FINAL. Applicant is reminded to identify claims 15, 17, and 18 as being withdrawn in the next submission of a claim listing.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1, lines , recites “a plurality of gate structures extending to pass the string selection line stack in the vertical direction,” which should read “a plurality of gate structures extending to pass through the string selection line stack in the vertical direction” for proper composition.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7-11, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moon et al. (US20200381449A1) in view of Choi et al. (US20240023332A1).
Regarding claim 1, Moon teaches in Fig. 2 an integrated circuit device comprising:
a semiconductor substrate (100) {[0026]};
a gate stack (125, WL1-WLn) comprising a plurality of gate layers (WL1-WLn) and a plurality of insulating layers (125), the plurality of gate layers (WL1-WLn) and the plurality of insulating layers (125) being alternately stacked on the semiconductor substrate (100) {[0028]};
a plurality of channel structures (CS2, CS4 in 125, WL1-WLn) extending to pass through the gate stack (125, WL1-WLn) in a vertical direction {[0039]};
a word line cut (WLC) extending to pass through the gate stack (125, WL1-WLn) in the vertical direction {[0035]};
a string selection line stack (SSL_L, SSL_U) on the gate stack (125, WL1-WLn) {[0027]}; and
a plurality of gate structures (CS2, CS4 in SSL_L, SSL_U) extending to pass [through] the string selection line stack (SSL_L, SSL_U) in the vertical direction, the plurality of gate structures (CS2, CS4 in SSL_L, SSL_U) completely overlapping the plurality of channel structures (CS2, CS4 in 125, WL1-WLn) corresponding thereto {[0039, 0041, 0044]}.
Moon does not teach
an inter-gate cutting film is between two adjacent gate structures, which are adjacent to each other in an oblique direction, from among the plurality of gate structures, and
the two adjacent gate structures are symmetrically positioned in a mirror-image relationship about the inter-gate cutting film.
In an analogous art, Choi teaches in Figs. 5, 6C, 7A and paragraphs [0056, 0069] an inter-gate cutting film (163) is between two adjacent gate structures ({[120A, upper 123A], [120B, upper 123B]}/{[120A, upper 123A, 161A], [120B, upper 123B, 161B]}), which are adjacent to each other in an oblique direction (DR4), from among a plurality of gate structures (multiple groups of {[120, upper 123]/[120, upper 123, 161]}), and the two adjacent gate structures are symmetrically positioned in a mirror-image relationship about the inter-gate cutting film (163). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moon’s integrated circuit device based on the teachings of Choi, to achieve the above-identified subject matter, so a memory cell string that is defined along the first channel structure … and a memory cell string that is defined along the second channel structure … may be controlled independently of each other. Choi [0059]. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Choi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Examiner’s Note: The American Heritage College Dictionary, fourth edition, defines “gate” as “[a] passageway.”
Regarding claim 2, Moon as modified by Choi teaches the integrated circuit device of claim 1, but Moon does not teach wherein a vertical level of an uppermost surface of the inter-gate cutting film is same as a vertical level of an uppermost surface of each of the plurality of gate structures.
Choi teaches in Fig. 6C and paragraphs [0056, 0069] a vertical level of an uppermost surface of the inter-gate cutting film (163) is same as a vertical level of an uppermost surface of each of the plurality of gate structures (multiple groups of [120, upper 123, 161]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moon’s integrated circuit device as modified by Choi based on the further teachings of Choi, to achieve the above-identified subject matter, so a memory cell string that is defined along the first channel structure … and a memory cell string that is defined along the second channel structure … may be controlled independently of each other. Choi [0059]. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Choi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 3, Moon as modified by Choi teaches the integrated circuit device of claim 1, and Moon further teaches wherein
each of the plurality of channel structures (CS2, CS4 in WL1-WLn) comprises,
a channel hole (hole housing 130, 132, 134 in WL1-WLn) {Fig. 2},
a first gate dielectric layer (132 in WL1-WLn) and a first channel layer (130 in WL1-WLn) sequentially on a sidewall of the channel hole (hole housing 130, 132, 134 in WL1-WLn) {Figs. 2, 3; [0039]},
a buried insulating layer (134 in WL1-WLn) filling a remaining space of the channel hole (hole housing 130, 132, 134 in WL1-WLn) {Figs. 2, 3; [0044]}, and
a conductive plug (136) configured to block an entrance of the channel hole (hole housing 130, 132, 134 in WL1-WLn) {Figs. 2, 3; [0045]}; and
each of the plurality of gate structures (CS2, CS4 in SSL_L, SSL_U) comprises:
a gate hole (hole housing CS2, CS4 in SSL_L, SSL_U) {Fig. 2},
a second channel layer (130 in SSL_L, SSL_U) and a second gate dielectric layer (132 in SSL_L, SSL_U) sequentially arranged on a sidewall of the gate hole (hole housing CS2, CS4 in SSL_L, SSL_U) {Fig. 2; [0039]}, and
a core gate layer (134 in SSL_L, SSL_U) filling a remaining space of the gate hole (hole housing CS2, CS4 in SSL_L, SSL_U) {Fig. 2; [0044]}.
Regarding claim 4, Moon as modified by Choi teaches the integrated circuit device of claim 3, but Moon does not teach wherein the inter-gate cutting film is in contact with respective ones of the second channel layers, respective ones of the second gate dielectric layers, and respective ones of the core gate layers of the two adjacent gate structures.
Choi teaches in Fig. 7A and paragraph [0069, 0070] an inter-gate cutting film (163) is in contact with respective ones of second channel layers (125A, 125B), respective ones of second gate dielectric layers (123A, 123B), and respective ones of core gate layers (129A, 129B) of two adjacent gate structures ([120A, upper 123A], [120B, upper 123B]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moon’s integrated circuit device as modified by Choi based on the further teachings of Choi, to achieve the above-identified subject matter, so a memory cell string that is defined along the first channel structure … and a memory cell string that is defined along the second channel structure … may be controlled independently of each other. Choi [0059]. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Choi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 5, Moon as modified by Choi teaches the integrated circuit device of claim 3, but Moon does not teach wherein one sidewall of the core gate layer is in contact with the inter-gate cutting film, and remaining sidewalls and a bottom surface of the core gate layer are surrounded by the second channel layer.
Choi teaches in Figs. 7A and 10B one sidewall of a core gate layer (129A/129B) is in contact with an inter-gate cutting film (163), and remaining sidewalls and a bottom surface of the core gate layer (129A/129B) are surrounded by a second channel layer (125A/125B) {Fig. 10A illustrates 125 surrounding outer side and bottom of 129}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moon’s integrated circuit device as modified by Choi based on the further teachings of Choi, to achieve the above-identified subject matter, so a memory cell string that is defined along the first channel structure … and a memory cell string that is defined along the second channel structure … may be controlled independently of each other. Choi [0059]. Moreover, all the claimed elements (e.g., sidewall, core gate layer, inter-gate cutting film, bottom surface, channel layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Choi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 7, Moon as modified by Choi teaches the integrated circuit device of claim 3, and Moon further teaches wherein a first lateral width of the channel hole of each of the plurality of channel structures is less than a second lateral width of the second channel layer of each of the plurality of gate structures.
Choi teaches in Fig. 6C a first lateral width of a channel hole (lower 123A/B, lower 127A/B) of each of a plurality of channel structures (multiple groups of [120, upper 123]) is less than a second lateral width of a second channel layer (120A/B, upper 123A/B) of each of the plurality of gate structures (multiple groups of [120, upper 123]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moon’s integrated circuit device as modified by Choi based on the further teachings of Choi, to achieve the above-identified subject matter, so a memory cell string that is defined along the first channel structure … and a memory cell string that is defined along the second channel structure … may be controlled independently of each other. Choi [0059]. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Choi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 8, Moon as modified by Choi teaches the integrated circuit device of claim 3, but Moon does not teach wherein,
in each of the plurality of gate structures,
an uppermost surface of the second channel layer, an uppermost surface of the second gate dielectric layer, and an uppermost surface of the core gate layer are coplanar with each other.
Choi teaches in Fig. 6C in each of a plurality of gate structures ([120A, upper 123A], [120B, upper 123B]), an uppermost surface of a second channel layer (125A/125B), an uppermost surface of a second gate dielectric layer (123A/123B), and an uppermost surface of a core gate layer (129A/129B) are coplanar with each other. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moon’s integrated circuit device as modified by Choi based on the further teachings of Choi, to achieve the above-identified subject matter, so a memory cell string that is defined along the first channel structure … and a memory cell string that is defined along the second channel structure … may be controlled independently of each other. Choi [0059]. Moreover, all the claimed elements (e.g., gate structure, channel layer, gate dielectric layer, core gate layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Choi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 9, Moon as modified by Choi teaches the integrated circuit device of claim 3, and Moon further teaches wherein, in a view from above, at least one sidewall of each of the plurality of gate structures (CS2, CS4 in SSL_L, SSL_U) has a rounded shape {Fig. 1}.
Regarding claim 10, Moon as modified by Choi teaches the integrated circuit device of claim 1, but Moon does not teach wherein the two adjacent gate structures share one inter-gate cutting film therebetween.
Choi teaches in Figs. 6C and 7A and paragraph [0068] two adjacent gate structures ([120A, upper 123A], [120B, upper 123B]) share one inter-gate cutting film (163) therebetween. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moon’s integrated circuit device as modified by Choi based on the further teachings of Choi, to achieve the above-identified subject matter, so a memory cell string that is defined along the first channel structure … and a memory cell string that is defined along the second channel structure … may be controlled independently of each other. Choi [0059]. Moreover, all the claimed elements (e.g., two adjacent gate structures, inter-gate cutting film) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Choi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 11, Moon teaches in Fig. 2 an integrated circuit device comprising:
a semiconductor substrate (100) {[0026]};
a gate stack (125, WL1-WLn) comprising a plurality of gate layers (WL1-WLn) and a plurality of insulating layers (125), the plurality of gate layers (WL1-WLn) and the plurality of insulating layers (125) being alternately stacked on the semiconductor substrate (100) {[0028]};
a plurality of channel structures (CS2, CS4 in 125, WL1-WLn) extending to pass through the gate stack (125, WL1-WLn) in a vertical direction {[0039]};
a word line cut (WLC) extending to pass through the gate stack (125, WL1-WLn) in the vertical direction {[0035]};
a string selection line stack (SSL_L, SSL_U) on the gate stack (125, WL1-WLn) {[0027]}; and
a plurality of gate structures (CS2, CS4 in SSL_L, SSL_U) extending to pass through the string selection line stack (SSL_L, SSL_U) in the vertical direction, the plurality of gate structures (CS2, CS4 in SSL_L, SSL_U) completely overlapping the plurality of channel structures (CS2, CS4 in 125, WL1-WLn) corresponding thereto {[0039, 0041, 0044]},
wherein each of the plurality of gate structures (CS2, CS4 in SSL_L, SSL_U) comprises a gate hole (hole housing CS2, CS4 in SSL_L, SSL_U), a channel layer (130 in SSL_L, SSL_U) and a gate dielectric layer (132 in SSL_L, SSL_U), and a core gate layer (134 in SSL_L, SSL_U), the channel layer (130 in SSL_L, SSL_U) and the gate dielectric layer (132 in SSL_L, SSL_U) being sequentially on a sidewall of the gate hole (hole housing CS2, CS4 in SSL_L, SSL_U), and the core gate layer (134 in SSL_L, SSL_U) filling a remaining space of the gate hole (hole housing CS2, CS4 in SSL_L, SSL_U) {Fig. 2; [0039, 0044]}two adjacent gate structures (CS2, CS4 in SSL_L, SSL_U), which are adjacent to each other in an oblique direction to the word line cut (WLC), from among the plurality of gate structures (CS2, CS4 in SSL_L, SSL_U) {Fig. 2; a particular direction of word line cut may be selected so as to be oblique to CS2, CS4 in SSL_L, SSL_U}.
Moon does not teach an inter-gate cutting film is between two adjacent gate structures, and the inter-gate cutting film is in contact with respective ones of the channel layers, respective ones of the gate dielectric layers, and respective ones of the core gate layers of the two adjacent gate structures.
Choi teaches in Figs. 5, 6C, 7A and paragraphs [0056, 0069] an inter-gate cutting film (163) is between two adjacent gate structures ([120A, upper 123A], [120B, upper 123B]), and the inter-gate cutting film (163) is in contact with respective ones of the channel layers (125A, 125B), respective ones of the gate dielectric layers (123A, 123B), and respective ones of the core gate layers (129A, 129B) of the two adjacent gate structures ([120A, upper 123A], [120B, upper 123B]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moon’s integrated circuit device based on the teachings of Choi, to achieve the above-identified subject matter, so a memory cell string that is defined along the first channel structure … and a memory cell string that is defined along the second channel structure … may be controlled independently of each other. Choi [0059]. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Choi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 14, Moon as modified by Choi teaches the integrated circuit device of claim 11, but Moon does not teach wherein, in a view from above, the inter-gate cutting film has a shape selected from the group of shapes consisting of a rectangular shape, a square shape, a circular shape, and an elliptical shape.
Choi teaches in Fig. 7A that in a view from above, an inter-gate cutting film (163) has a rectangular shape. The motivation for this modification is identified with respect to base claim 11. Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 12 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moon in view of Choi as applied to claim 11 above, and further in view of Song et al. (US20210398593A1).
Regarding claim 12, Moon as modified by Choi teaches the integrated circuit device of claim 11, and Moon further teaches wherein
each of the plurality of channel structures (CS2, CS4 in WL1-WLn) comprises:
a channel hole (hole housing 130, 132, 134 in WL1-WLn) {Fig. 2};
a material layer (132 in WL1-WLn) and a vertical channel layer (130 in WL1-WLn) sequentially on a sidewall of the channel hole (hole housing 130, 132, 134 in WL1-WLn) {Figs. 2, 3; [0039]};
a buried insulating layer (134 in WL1-WLn) filling a remaining space of the channel hole (hole housing 130, 132, 134 in WL1-WLn) {Figs. 2, 3; [0044]}; and
a conductive plug (136) configured to block an entrance of the channel hole (hole housing 130, 132, 134 in WL1-WLn) {Figs. 2, 3; [0045]}.
Moon does not disclose the material layer is a ferroelectric material layer.
In an analogous art, Song teaches in Fig. 3A and paragraph [0080] a ferroelectric material layer (322) and a vertical channel layer (321) sequentially on a sidewall of a channel hole (hole for 320-324). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moon’s integrated circuit device as modified by Choi based on the teachings of Song, to achieve the above-identified subject matter, because all the claimed elements (e.g., ferroelectric material layer, channel layer, channel hole) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Song) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 16, Moon as modified by Choi teaches the integrated circuit device of claim 11, but Moon does not teach wherein, in each of the plurality of gate structures (CS2, CS4 in SSL_L, SSL_U), a vertical level of an uppermost surface of the channel layer (130 in SSL_L, SSL_U) is substantially the same as a vertical level of an uppermost surface of the gate dielectric layer (132 in SSL_L, SSL_U).
Moon as modified by Choi does not teach a vertical level of an uppermost surface of the core gate layer is lower than the vertical level of the uppermost surface of the channel layer.
Song teaches in Fig. 3A a vertical level of an uppermost surface of a core gate layer (324) is lower than the vertical level of the uppermost surface of a channel layer (321). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moon’s integrated circuit device as modified by Choi based on the teachings of Song, to achieve the above-identified subject matter, because all the claimed elements (e.g., uppermost surface, core gate layer, channel layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Song) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moon in view of Choi as applied to claim 11 above, and further in view of Park (US20140321193A1).
Regarding claim 13, Moon as modified by Choi teaches the integrated circuit device of claim 11, and Moon further teaches wherein each of the plurality of channel structures (CS2, CS4 in WL1-WLn) comprises:
a channel hole (hole housing 130, 132, 134 in WL1-WLn) {Fig. 2};
a vertical channel layer (130 in WL1-WLn) and a material layer (132 in WL1-WLn) sequentially on a sidewall of the channel hole (hole housing 130, 132, 134 in WL1-WLn) {Figs. 2, 3; [0039]};
a buried insulating layer (134 in WL1-WLn) filling a remaining space of the channel hole (hole housing 130, 132, 134 in WL1-WLn) {Figs. 2, 3; [0044]}; and
a conductive plug (136) configured to block an entrance of the channel hole (hole housing 130, 132, 134 in WL1-WLn) {Figs. 2, 3; [0045]}.
Moon does not teach the material layer is a variable resistive material layer.
In an analogous art, Park teaches in Fig. 10 and paragraph [0043] a vertical channel layer (160) and a variable resistive material layer (180) sequentially on a sidewall of a channel hole (150). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moon’s integrated circuit device as modified by Choi based on the teachings of Park, to achieve the above-identified subject matter, because all the claimed elements (e.g., variable resistive material layer, channel layer, channel hole) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Song) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moon in view of Park et al. (US20220344366A1) and Choi.
Regarding claim 19, Moon teaches in Fig. 2 an electronic system comprising:
an integrated circuit device comprises:
a semiconductor substrate (100) {[0026]};
a gate stack (125, WL1-WLn) comprising a plurality of gate layers (WL1-WLn) and a plurality of insulating layers (125), the plurality of gate layers (WL1-WLn) and the plurality of insulating layers (125) being alternately stacked on the semiconductor substrate (100) {[0028]};
a plurality of channel structures (CS2, CS4 in 125, WL1-WLn) extending to pass through the gate stack (125, WL1-WLn) in a vertical direction {[0039]};
a word line cut (WLC) extending to pass through the gate stack (125, WL1-WLn) in the vertical direction {[0035]};
a string selection line stack (SSL_L, SSL_U) on the gate stack (125, WL1-WLn) {[0027]}; and
a plurality of gate structures (CS2, CS4 in SSL_L, SSL_U) extending to pass through the string selection line stack (SSL_L, SSL_U) in the vertical direction, the plurality of gate structures (CS2, CS4 in SSL_L, SSL_U) completely overlapping the plurality of channel structures (CS2, CS4 in 125, WL1-WLn) corresponding thereto {[0039, 0041, 0044]}.
Moon does not teach a main substrate; an integrated circuit device on the main substrate; and a controller electrically connected to the integrated circuit device on the main substrate.
In an analogous art, Park ‘366 teaches in Fig. 10 and paragraph [0079] a main substrate (1000); an integrated circuit device (1200) on the main substrate (1000); and a controller (1100) electrically connected to the integrated circuit device (1200) on the main substrate (1000). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moon’s electronic system based on the teachings of Park, to achieve the above-identified subject matter, so the memory device … may perform a program operation, a read operation, and an erase operation in response to control of the controller. Park ‘366 [0084].
Moon as modified by Park does not teach wherein an inter-gate cutting film is between two adjacent gate structures, which are adjacent to each other in an oblique direction, from among the plurality of gate structures, and the two adjacent gate structures are symmetrically positioned in a mirror-image relationship about the inter-gate cutting film.
Choi teaches in Figs. 5, 6C, 7A and paragraphs [0056, 0069] an inter-gate cutting film (163) is between two adjacent gate structures ([120A, upper 123A], [120B, upper 123B]), which are adjacent to each other in an oblique direction (DR4), from among a plurality of gate structures (multiple groups of 120, upper 123), and the two adjacent gate structures ([120A, upper 123A], [120B, upper 123B]) are symmetrically positioned in a mirror-image relationship about the inter-gate cutting film (163). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moon’s electronic system as modified by Park based on the teachings of Choi, to achieve the above-identified subject matter, so a memory cell string that is defined along the first channel structure … and a memory cell string that is defined along the second channel structure … may be controlled independently of each other. Choi [0059].
Regarding claim 20, Moon as modified by Park ‘366 and Choi teaches the electronic system of claim 19, and Moon further teaches wherein
each of the plurality of gate structures (CS2, CS4 in SSL_L, SSL_U) comprises a gate hole (hole housing CS2, CS4 in SSL_L, SSL_U), a channel layer (130 in SSL_L, SSL_U), a gate dielectric layer (132 in SSL_L, SSL_U), and a core gate layer (134 in SSL_L, SSL_U), the channel layer (130 in SSL_L, SSL_U) and the gate dielectric layer (132 in SSL_L, SSL_U) being sequentially [arranged] on a sidewall of the gate hole (hole housing CS2, CS4 in SSL_L, SSL_U), and the core gate layer (134 in SSL_L, SSL_U) filling a remaining space of the gate hole (hole housing CS2, CS4 in SSL_L, SSL_U) {Fig. 2; [0039, 0044]}.
Moon does not teach the main substrate further comprises wiring patterns configured to electrically connect the integrated circuit device to the controller.
Park ‘366 teaches in Fig. 10 and paragraph [0083] wiring patterns (e.g., input/output lines) configured to electrically connect an integrated circuit device (1200) to a controller (1100). The motivation for this modification is identified with respect to base claim 19.
Moon as modified by Park ‘366 does not teach the inter-gate cutting film is in contact with respective ones of the channel layers, respective ones of the gate dielectric layers, and respective ones of the core gate layers of the two adjacent gate structures.
Choi teaches in Fig. 7A and paragraph [0069, 0070] an inter-gate cutting film (163) is in contact with respective ones of channel layers (125A, 125B), respective ones of gate dielectric layers (123A, 123B), and respective ones of core gate layers (129A, 129B) of two adjacent gate structures ([120A, upper 123A], [120B, upper 123B]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Moon’s electronic system as modified by Park ‘366 and Choi based on the further teachings of Choi, to achieve the above-identified subject matter, so a memory cell string that is defined along the first channel structure … and a memory cell string that is defined along the second channel structure … may be controlled independently of each other. Choi [0059].
Allowable Subject Matter
Claims 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding dependent claim 6, the prior art does not teach, suggest or motivate one having ordinary skill in the art to have the recited subject matter whereby “each of the plurality of gate structures comprises: an upper bit line contact in contact with an uppermost surface of the second channel layer in the vertical direction; and an upper word line contact in contact with an uppermost surface of the core gate layer in the vertical direction” in combination with the other limitations of the claim.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jung et al. (US20230301091A1) teaches a semiconductor device includes: a gate structure including conductive layers and insulating layers, which are alternately stacked; a plurality of channel structures penetrating the gate structure, the plurality of channel structures being arranged in a first direction; a plurality of cutting structures each isolating each of the plurality of channel structures, respectively, into a plurality of divided channel structures while penetrating each of the plurality of channel structures, respectively; and a plurality of interconnection lines located over the gate structure and extending in the first direction. Each of the plurality of cutting structures has substantially a cross (+) shape including extension parts extending in directions oblique to the first direction.
Conclusion
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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