DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on Jul. 30th 2026 is acknowledged. Claims 1-15 are examined in this office action. Claims 16-20 are withdrawn from further consideration.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-5 and 14 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Sun et al. (US 20200194447), hereinafter Sun.
Regarding claim 1, Sun teaches a device structure (Abstract), comprising:
an alternating stack (fig. 16A, film stack 335; para. 0061) of insulating layers (dielectric layer 450; para. 0072) and electrically conductive layers (control gates 333 and LSG 332; para. 0061), wherein the electrically conductive layers (332, 333) comprise a vertically neighboring pair of a first-type electrically conductive layer (332) and a second-type electrically conductive layer (333) that overlies the first-type electrically conductive layer (332);
a dielectric material portion (barrier layer 664 made of dielectric layer; para. 0089) overlying the alternating stack (335);
memory openings (memory strings 212; para. 0057) vertically extending through the alternating stack (335);
memory opening fill structures (memory film 337, channel layer 338, core filling film 339; para. 0061) located in the memory openings (212), wherein each of the memory opening fill structures (337, 338, 339) comprises a respective vertical stack of memory elements (337) and vertical semiconductor channel (338); and
a coaxial double contact via structure (coaxial contact structure 1696; para. 0129) vertically extending through the dielectric material portion (664) and comprising:
an inner layer contact via structure (conductive core 1694; para. 0129) contacting the first-type electrically conductive layer (332);
at least one insulating spacer layer (insulating ring 1590; para. 0129) comprising a respective tubular insulating portion (1590 has a ring shape) that laterally surrounds the inner layer contact via structure (1694); and
an outer layer contact via structure (conductive ring 1384; para. 0129) comprising a tubular conductive portion (1387 has a ring shape) that laterally surrounds the at least one insulating spacer layer (1590) and contacting the second-type electrically conductive layer (333).
Regarding claim 2, Sun further teaches the device structure of Claim 1, wherein a bottom surface of the inner layer contact via structure (fig. 16A, bottom surface of 1694) contacts a horizontal surface segment of the first-type electrically conductive layer (horizontal surface of 332).
Regarding claim 4, Sun further teaches the device structure of Claim 1, wherein a cylindrical surface segment of an outer sidewall of the outer layer contact via structure (fig. 16A-B, cylindrical bottom surface of outer side of 1384) contacts a cylindrical surface of the second-type electrically conductive layer (cylindrical top surface of 333).
Regarding claim 5, Sun further teaches the device structure of Claim 1, wherein:
a first insulating layer (fig. 16A, 450 between 332, 333) of the insulating layers (450) is located between the first-type electrically conductive layer (332) and the second-type electrically conductive layer (333); and
a cylindrical surface segment of a sidewall of the inner layer contact via structure (cylindrical surface of 1694) contacts a cylindrical sidewall surface of the first insulating layer (cylindrical surface of 450 between 332, 333).
Regarding claim 14, Sun further teaches the device structure of Claim 1, further comprising a contact-level dielectric layer (fig. 16A, first insulating layer 768; para. 0090) overlying the alternating stack (335) and the dielectric material portion (664), wherein a topmost surface of the inner layer contact via structure (topmost surface of 1694), a topmost surface of the at least one insulating spacer layer (topmost surface of 1590), and a topmost surface of the outer layer contact via structure (topmost surface of 1384) are located within a horizontal plane (same top surface) including a top surface of the contact-level dielectric layer (top surface of 768).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Sun in view of Tanaka et al. (US 20130154096).
Regarding claim 3, Sun teaches the device structure of Claim 2 including the first-type electrically conductive layer (fig. 16A, 332).
Sun fails to explicitly teach the horizontal surface segment of the first-type electrically conductive layer is vertically recessed relative a top surface of the first-type electrically conductive layer.
However, Tanaka teaches the horizontal surface segment of the first-type electrically conductive layer (Tanaka: fig. 5, the horizontal surface of copper conductive layer 15; para. 0043, similar to 332 of Sun) is vertically recessed (Tanaka: recessed under conductive plug 31; para. 0061) relative a top surface of the first-type electrically conductive layer (Tanaka: top surface of 15).
Tanaka and Sun are considered to be analogous to the claimed invention because they are in the same field of contact structures.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the horizontal surface segment of the first-type electrically conductive layer is vertically recessed as taught by Tanaka.
Doing so would realize recess surface of conductive layer, which is normal from etching, and the electromigration resistance of the bottom of the conductive plug decreases (Tanaka: para. 0014).
Claims 6-8, 11-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Sun in view of Yazawa et al. (US 20180226341).
Regarding claim 6, Sun further teaches the device structure of Claim 5 including the at least one insulating spacer layer (fig. 16A, 1590).
Sun fails to explicitly teach the at least one insulating spacer layer comprises a stepped annular bottom surface contacting the first insulating layer.
However, Yazawa teaches the at least one insulating spacer layer (Yazawa: fig. 1B, middle insulating films 42, conductive films 41 and 42; para. 0017, similar to 1590 of Sun) comprises a stepped annular bottom surface (Yazawa: stepped annular bottom surface of 42/41/42) contacting the first insulating layer (Yazawa: second insulating layers 22; para. 0014, similar to 450 of Sun).
Yazawa and Sun are considered to be analogous to the claimed invention because they are in the same field of memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the at least one insulating spacer layer comprises a stepped annular bottom surface as taught by Yazawa.
Doing so would realize contact with more layers that the use efficiency of the contact can be increased (Yazawa: para. 0044).
Regarding claim 7, Sun in view of Yazawa further teaches the device structure of Claim 6, wherein the stepped annular bottom surface (Yazawa: fig. 1B, bottom surface of middle 42/41/42) comprises:
an inner annular horizontal surface segment (Yazawa: inner horizontal surface of 42);
an outer annular horizontal surface segment (Yazawa: outer horizontal surface of 42); and
a cylindrical vertical surface segment (Yazawa: middle cylindrical surface with vertical surface of 41 and 42) that connects an inner periphery of the outer annular horizontal surface segment (Yazawa: inner periphery of outer horizontal surface of 42) to an outer periphery of the inner annular horizontal surface segment (Yazawa: outer periphery of inner horizontal surface of 42).
Regarding claim 8, Sun teaches the device structure of Claim 1 including the at least one insulating spacer layer (fig. 16A, 1590).
Sun fails to explicitly teach the at least one insulating spacer layer comprises:
an inner insulating spacer layer; and
an outer insulating spacer layer laterally surrounding the inner insulating spacer layer.
However, Yazawa teaches the at least one insulating spacer layer (Yazawa: fig. 1B, middle insulating films 42, conductive films 41 and 42; para. 0017, similar to 1590 of Sun) comprises:
an inner insulating spacer layer (Yazawa: inner 42); and
an outer insulating spacer layer (Yazawa: outer 42) laterally surrounding the inner insulating spacer layer (Yazawa: inner 42).
Yazawa and Sun are considered to be analogous to the claimed invention because they are in the same field of memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add an inner insulating spacer layer and an outer insulating spacer layer as taught by Yazawa.
Doing so would realize contact with more layers that the use efficiency of the contact can be increased (Yazawa: para. 0044).
Regarding claim 11, Sun further teaches the device structure of Claim 1, wherein:
a first insulating layer (fig. 16A, 450 between 332, 333) of the insulating layers (450) is located between the first-type electrically conductive layer (332) and the second-type electrically conductive layer (333); and
the outer layer contact via structure (1384 has a TiN/W/TiN, TiN outside and W inside layers; para. 0116) comprises an outer metallic barrier liner (TiN) and an outer metal layer (W), wherein
Sun fails to explicitly teach the outer metallic barrier liner contacts a cylindrical sidewall of the second-type electrically conductive layer and an annular surface of the first insulating layer.
However, Yazawa teaches the outer metallic barrier liner (Yazawa: fig. 1B, conductive films 41; para. 0017, similar to 1384 of Sun with TiN) contacts a cylindrical sidewall of the second-type electrically conductive layer (Yazawa: cylindrical sidewall of second conductive layers 21; para. 0014, similar to 333 of Sun) and an annular surface of the first insulating layer (Yazawa: annular top surface of second insulating layers 22; para. 0014, similar to 450 of Sun).
Yazawa and Sun are considered to be analogous to the claimed invention because they are in the same field of memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the outer metallic barrier liner contacts a cylindrical sidewall of the second-type electrically conductive layer and an annular surface of the first insulating layer as taught by Yazawa.
Doing so would realize contact with more layers that the use efficiency of the contact can be increased (Yazawa: para. 0044).
Regarding claim 12, Sun in view of Yazawa further teaches the device structure of Claim 11, wherein the outer metal layer (Sun: fig. 16A, W of 1384, at least bottom part or indirectly contacts) contacts a cylindrical surface of the at least one insulating spacer layer (Sun: cylindrical surface of 1590).
Regarding claim 13, Sun in view of Yazawa further teaches the device structure of Claim 11, wherein the inner layer contact via structure (Sun: fig. 16A, 1694 has a TiN/W/TiN, TiN outside and W inside layers; para. 0116) comprises an inner metallic barrier liner (Sun: TiN) and an inner metal layer (Sun: W), wherein the inner metallic barrier liner (Sun: W of 1694) contacts a planar surface of the first-typer electrically conductive layer (Sun: planar surface of 332) and a cylindrical surface of the at least one insulating spacer layer (Sun: cylindrical surface of 1590).
Regarding claim 15, Sun further teaches the device structure of Claim 1, further comprising a contact-level dielectric layer (fig. 16A, first insulating layer 768; para. 0090) overlying the alternating stack (355) and the dielectric material portion (664).
Sun fails to explicitly teach the at least one insulating spacer layer comprises a laterally-extending portion that overlies the contact-level dielectric layer.
However, Yazawa teaches the at least one insulating spacer layer (Yazawa: fig. 1B, insulating films 42; para. 0017, similar to 1590 of Sun) comprises a laterally-extending portion (Yazawa: 42 extent laterally) that overlies the contact-level dielectric layer (interlayer insulating film 30; para. 0023, similar to 768 of Sun).
Yazawa and Sun are considered to be analogous to the claimed invention because they are in the same field of memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the at least one insulating spacer layer comprises a laterally-extending portion that overlies the contact-level dielectric layer as taught by Yazawa.
Doing so would realize contact with more layers that the use efficiency of the contact can be increased (Yazawa: para. 0044).
Allowable Subject Matter
Claims 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
The prior art fails to teach or clearly suggest the limitations stating:
"the inner insulating spacer layer comprises a laterally protruding annular bottom portion having a cylindrical sidewall surface that contacts a lower cylindrical surface segment of an inner sidewall of the outer layer contact via structure" as cited in claim 9.
Claim 10 is allowable for being dependent on claim 9.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
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/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818
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