Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 4 in the reply filed on 7/28/2026 is acknowledged.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 34-, 39, 42-43 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Warabino et al. (US 20120223406 A1).
PNG
media_image1.png
662
478
media_image1.png
Greyscale
CLAIM 34. Warabino teaches the semiconductor circuit structure comprising:
a semiconductor substrate 10 with an original semiconductor surface (Fig. 8);
a set of active regions 23 within the semiconductor substrate (Fig. 8);
a first shallow trench isolation (STI) region 16/13 neighboring to the set of active regions 23;
a transistor is located within a first active region of the set of active region, wherein the transistor comprises a gate structure 25, a source region 24, and a drain region 24 (Fig. 8);
a heat removing layer 14 within the STI region 16/13, wherein the thermal conductivity of the heat removing layer is higher than that of SiO2 ( ¶52+ - Si & Tungsten) and
a top insulating layer over the heat removing layer 51, wherein the first STI region further includes a bottom insulating layer 13 under the heat removing layer 14, and the heat removing layer is isolated from the source region and the drain region of the transistor (by isolation material 13 and 16) .
CLAIM 35. Warabino teaches the semiconductor circuit structure of claim 34, wherein a top surface of the heat removing layer is close to the original semiconductor surface of the semiconductor substrate (Fig. 8).
CLAIM 36. Warabino teaches the semiconductor circuit structure of claim 35, wherein the heat removing layer surrounds the transistor and is an electrical insulator during the operation of the semiconductor circuit structure (Fig. 8).
CLAIM 37. Warabino teaches the semiconductor circuit structure of claim 34, wherein the heat removing layer comprises a semiconductor material (Si - Fig. 8).
CLAIM 38. Warabino teaches the semiconductor circuit structure of claim 36, wherein the semiconductor material comprises BN, AIN, SiC, SiGe, Si, or the combination thereof (Si - Fig. 8 & ¶52).
CLAIM 39. Warabino teaches the semiconductor circuit structure of claim 34, wherein a first thin oxide layer 13 is between a sidewall of the drain region of the transistor, and a second thin oxide layer 13 is between a sidewall of the source region of the transistor; wherein the heat removing layer is isolated from the drain region of the transistor by the top insulating layer 51, the bottom insulating layer 13, and the first thin oxide layer 13, and the heat removing layer is isolated from the source region of the transistor by the top insulating layer 51, the bottom insulating layer 13, and the second thin oxide layer 13 (Fig. 8).
CLAIM 42. Warabino teaches the semiconductor circuit structure of claim 34, wherein the first STI region surrounds the set of active regions (Fig. 8).
CLAIM 43. Warabino teaches the semiconductor circuit structure of claim 42, wherein the heat removing layer is positioned under the original semiconductor surface, and the heat removing layer surrounds a peripheral border of the set of active regions (Fig. 8).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 40-41 is/are rejected under 35 U.S.C. 103 as being unpatentable over Warabino et al. (US 20120223406 A1) in view of Goo et al. (US 20030189231 A1)
CLAIM 40. Warabino teaches semiconductor circuit structure of claim 34, however is silent upon wherein the drain region of the transistor includes a lightly-doped region laterally extending from a sidewall of the semiconductor substrate and a heavily-doped region laterally extending from the sidewall of the lightly-doped region. Warabino describes a generic transistor structure that would have been recognized by a person of ordinary skill in the art (PHOSITA) to optionally comprise lightly doped drain (LDD) regions. LDD regions were notoriously well-known doping profiles commonly utilized for threshold voltage adjustments and the optimization of transistor properties.
For evidence of this conventional knowledge, see Goo et al. (Fig. 3M), which demonstrates an analogous transistor having an engineered doping profile that includes LDD regions (68) adjacent to source/drain regions (72). It would have been obvious to a PHOSITA at the time of the invention to modify the transistor of Warabino with the LDD teaching of Goo. Applying a known technique, such as adding LDD regions, to a known device to yield predictable results in optimizing transistor operation is prima facie obvious (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385).
CLAIM 41. Warabino teaches the semiconductor circuit structure of claim 40, further comprising a metal contact connected to the top of the drain region and connected to a most lateral sidewall of the drain region (Fig. 8).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
JARRETT J. STARK
Primary Examiner
Art Unit 2822
8/13/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
Prosecution Insights