DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "a width of the dielectric fence in the second direction is less than a width of the dummy dielectric layer in the second direction" in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. As shown in fig. 1G of the application, the width of the dielectric fence 240 along D2 is from top to bottom and clearly greater than the width of each block of 270 along D2. For examination purposes, examiner has interpreted "a width of the dielectric fence in the second direction is less than a width of the dummy dielectric layer in the second direction" to be read as "a width of the dielectric fence in the first direction is less than a width of the dummy dielectric layer in the first direction". Claim 3 would also be rejected under 35 U.S.C. 112(b) because they are dependent on claim 2.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 8-9 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 20220139927 from IDS) in view of Young et al. (KR 20080091635).
Regarding claim 1, Chang teaches a semiconductor device (Abstract), comprising:
an active pattern (fig. 3, cell active region ACT; para. 0032);
a gate structure (fig. 7, cell gate structures 110; para. 0042) that extends in a first direction (first direction D1; para. 0041) on the active pattern (ACT);
a bit line (bit line structures 140ST; para. 0042) electrically connected to the active pattern (ACT) and extending in a second direction (second direction D2; para. 0041) that intersects the first direction (D1);
a gate contact (cell gate contact plug 262; para. 0124) electrically connected to the gate structure (110);
a dummy line (dummy bit line structure 140ST_1; para. 0071) between the gate contact (262) and the bit line (140ST).
Chang fails to teach a dummy dielectric layer at least partially surrounded by the dummy line,
wherein the dummy line comprises:
a first dummy line part between the dummy dielectric layer and the bit line;
a second dummy line part spaced apart from the first dummy line part; and
a plurality of connection parts that electrically connect the first and second dummy line parts to each other, and
wherein the dummy dielectric layer is between the first dummy line part and the second dummy line part and is between the plurality of connection parts.
However, Young teaches a dummy dielectric layer (Young: fig. 3, 4a, interlayer insulating film IDL3; para. 0010) at least partially surrounded (Young: fig. 4a, IDL3 fill in the middle opening surrounded by dBL) by the dummy line (Young: dummy bit line dBL; para. 0008, similar to 140ST_1 of Chang),
wherein the dummy line (Young: dBL) comprises:
a first dummy line part (Young: fig. 4a, bottom dBL) between the dummy dielectric layer (Young: middle opening IDL3) and the bit line (Chang: 140ST as lines next to dBL of Young);
a second dummy line part (Young: top dBL) spaced apart from the first dummy line part (Young: bottom dBL); and
a plurality of connection parts (Young: vertical connect of top and bottom dBL) that electrically connect the first and second dummy line parts (Young: top and bottom dBL) to each other, and
wherein the dummy dielectric layer (Young: IDL3) is between the first dummy line part (Young: bottom dBL) and the second dummy line part (Young: top dBL) and is between the plurality of connection parts (Young: vertical connect).
Young and Chang are considered to be analogous to the claimed invention because they are in the same field of memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a dummy dielectric layer at least partially surrounded by the dummy line as taught by Young.
Doing so would realize the mesh structure of dummy lines with openings to improve interlayer insulation to prevent deterioration of operating characteristics of the device (Young: para. 0023).
Regarding claim 2, Chang in view of Young further teaches the semiconductor device of claim 1, further comprising a dielectric fence (Chang: fig. 7, cell line spacer 154 between 140ST_1 and 140ST; para. 0067) between the first dummy line part (Young: bottom dBL as the right side of 140ST_1 of Chang) and the bit line (Chang: 140ST), wherein a width of the dielectric fence (Chang: width of 154) in the second direction is less than a width of the dummy dielectric layer (Young: width of ILD3 between dBL, which is around 1/3 of width of 140ST_1) in the second direction.
Regarding claim 3, Chang in view of Young further teaches the semiconductor device of claim 2, wherein:
the gate structure (Chang: fig. 7, 110) comprises a gate electrode layer (Chang: cell gate electrode 112; para. 0049) and a gate capping layer (Chang: cell gate capping pattern 113; para. 0049) on the gate electrode layer (Chang: 112), and
the dielectric fence (Chang: 154) and the dummy dielectric layer (Young: ILD3, similar to 154 between/within 140ST_1) contact the gate capping layer (Chang: 113).
Regarding claim 4, Chang in view of Young further teaches the semiconductor device of claim 1, wherein:
the gate structure (Chang: fig. 7, 110) comprises a plurality of gate structures (Chang: fig. 3, 112 correspond to word line WL; para. 0049), and
the dummy dielectric layer (Young: ILD3 replace storage node contact plug SNCP in the middle; para. 0020, and at least the top part of ILD3) overlaps the plurality of gate structures (Young: line dWL here also real word lines; para. 0020, similar to WL of Chang) in a third direction (Chang: vertical direction as D3) that intersects the first direction (Chang: D1) and the second direction (Chang: D2).
Regarding claim 5, Chang in view of Young further teaches the semiconductor device of claim 1, further comprising a dummy line capping layer (Chang: fig. 7, cell line capping film 144; para. 0071) on the dummy line (Chang: 140ST_1), wherein the dummy line capping layer (Chang: 144 on 140ST_1) at least partially surrounds the dummy dielectric layer (Young: on the dBL surrounds ILD3 in the middle).
Regarding claim 8, Chang teaches a semiconductor device (Abstract), comprising:
a substrate (fig. 2, substrate 100; para. 0032) that comprises a cell region (cell region 20; para. 0030), a peripheral region (peri region 24; para. 0030) at least partially surrounding the cell region (20), and an interface region (cell region isolation film 22; para. 0030) between the cell region (20) and the peripheral region (24);
an active pattern (fig. 3, cell active region ACT; para. 0032) on the substrate (100);
a gate structure (fig. 7, cell gate structures 110; para. 0042) on the active pattern (ACT);
a bit line (bit line structures 140ST; para. 0042) electrically connected to the active pattern (ACT);
a dummy line (dummy bit line structure 140ST_1; para. 0071) on the interface region (22);
a first outer dummy spacer (cell line spacers 151; para. 0067) that contacts a first outer sidewall (right sidewall) of the dummy line (140ST_1);
a second outer dummy spacer (second cell boundary spacer 246_2; para. 0072) that contacts a second outer sidewall (left sidewall) of the dummy line (140ST_1).
Chang fails to teach an inner dummy spacer that contacts inner sidewalls of the dummy line,
wherein the inner dummy spacer is between the first outer dummy spacer and the second outer dummy spacer.
However, Young teaches an inner dummy spacer (Young: fig. 5, spacer SP; para. 0022) that contacts inner sidewalls of the dummy line (Young: inner sidewalls of dummy bit line dBL; para. 0008, similar to 140ST_1 of Chang),
wherein the inner dummy spacer (Young: SP) is between the first outer dummy spacer and the second outer dummy spacer (Young: outside SP, similar to 151 and 246_2 of Chang).
Young and Chang are considered to be analogous to the claimed invention because they are in the same field of memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add an inner dummy spacer as taught by Young.
Doing so would realize the mesh structure of dummy lines with openings to improve interlayer insulation to prevent deterioration of operating characteristics of the device (Young: para. 0023).
Regarding claim 9, Chang in view of Young further teaches the semiconductor device of claim 8, wherein the inner dummy spacer (Young: fig. 4a, 5, SP) comprises:
a plurality of first parts (Young: SP along vertical connect of top and bottom dBL) that extend in a first direction (vertical); and
a plurality of second parts (Young: SP along dBL) that extend in a second direction (horizontal) intersecting the first direction (vertical),
wherein the plurality of first parts of the inner dummy spacer (Young: SP along vertical connect of top and bottom dBL) are spaced apart from each other (Young: spaced apart from left and right vertical connect) in the second direction,
wherein the plurality of second parts of the inner dummy spacer (Young: SP along dBL) are spaced apart from each other (Young: spaced apart from top dBL and bottom dBL) in the first direction, and
wherein one of the plurality of first parts of the inner dummy spacer (Young: SP along dBL) contacts respective ones of the second parts of the inner dummy spacer (Young: SP along vertical connect of top and bottom dBL).
Regarding claim 11, Chang in view of Young further teaches the semiconductor device of claim 8, wherein the dummy line comprises:
a first dummy line part (Young: fig. 4a, bottom dBL) and a second dummy line part (Young: top dBL) that are spaced apart from each other (Young: top and bottom dBL are spaced apart); and
a plurality of connection parts (Young: vertical connect of top and bottom dBL) that electrically connect the first dummy line part and the second dummy line part (Young: top and bottom dBL) to each other,
wherein the inner sidewalls of the dummy line (Young: inner sidewalls of dBL) comprise an inner sidewall of the first dummy line part (Young: inner sidewall of bottom dBL), an inner sidewall of the second dummy line part (Young: inner sidewall of top dBL), and inner sidewalls of the connection parts (Young: inner sidewall of vertical connect dBL), and
wherein the inner dummy spacer (Young: SP) contacts the inner sidewall of the first dummy line part, the inner sidewall of the second dummy line part, and the inner sidewalls of the connection parts (Young: inner sidewall of dBL).
Regarding claim 12, Chang in view of Young further teaches the semiconductor device of claim 11, wherein:
the first dummy line part (Young: fig. 4a, bottom dBL) is between the first outer dummy spacer (Chang: 151 at bottom outside of dBL of Young) and the inner dummy spacer (SP),
the second dummy line part (Young: top dBL) is between the second outer dummy spacer (Chang: 246_2 at top outside of dBL of Young) and the inner dummy spacer (SP), and
the plurality of connection parts (Young: vertical connect of top and bottom dBL) are between the first outer dummy spacer (Chang: 151) and the second outer dummy spacer (Chang: 246_2).
Regarding claim 13, Chang in view of Young further teaches the semiconductor device of claim 11, wherein:
the first dummy line part (Young: annotated fig. 4a, bottom dBL) and the second dummy line part (Young: top dBL) are spaced apart from each other in a first direction (vertical), and
a sum of a width of the first dummy line part in the first direction and a width in the first direction of the second dummy line part (Young: total width of top and bottom dBL as two solid arrow icons) is less than a width of one of plurality of the connection parts (Young: width of vertical connect of dBL as one dash arrow icon) in the first direction.
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279
343
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(annotated fig. 4a of Young)
Regarding claim 14, Chang in view of Young further teaches the semiconductor device of claim 11, wherein a distance (Young: annotated fig. 4a, solid diagonal arrow icon) between the first dummy line part (Young: bottom dBL) and the bit line (Young: BL here next to dBL) is greater than a distance (Young: vertical dot arrow icon) between the plurality of connection parts (Young: vertical connect of dBL) and the bit line (Young: BL).
Regarding claim 15, Chang in view of Young further teaches the semiconductor device of claim 8, further comprising a dummy dielectric layer (Young: fig. 3, 4a, interlayer insulating film IDL3; para. 0010) at least partially surrounded (Young: fig. 4a, IDL3 fill in the middle opening surrounded by dBL) by the inner dummy spacer (Young: SP within dBL).
Claims 6-7, 10 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Young as applied to claim 1 or 8 above, and further in view of Feng et al. (US 9859283).
Regarding claim 6, Chang in view of Young teaches the semiconductor device of claim 1 including the first dummy line part (Young: fig. 4a, bottom dBL).
Chang in view of Young fails to explicitly teach a width of the first dummy line part in the first direction is the same as a width of the bit line in the first direction.
However, Feng teaches a width of the first dummy line part (Feng: fig. 6A, width of line portion 162b of dummy bit line 160; col. 6, lin. 2-4, similar to 140ST_1 and left 140ST of Chang) in the first direction (horizontal) is the same as a width of the bit line (Feng: width of bit lines 150) in the first direction (horizontal).
Feng, Young and Chang are considered to be analogous to the claimed invention because they are in the same field of memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have more bit line as dummy line with same width of bit lines as taught by Feng.
Doing so would realize a method to form dummy lines with the bit lines more precisely, and the process yield is improved (Feng: col. 7, lin. 30-33).
Regarding claim 7, Chang in view of Young teaches the semiconductor device of claim 1 including the first dummy line part (Young: fig. 4a, bottom dBL).
Chang in view of Young fails to explicitly teach a width of the first dummy line part in the first direction is less than a width of the second dummy line part in the first direction.
However, Feng teaches a width of the first dummy line part (Feng: fig. 6A, width of line portion 162b of dummy bit line 160; col. 6, lin. 2-4, similar to left 140ST of Chang) in the first direction (horizontal) is less than a width of the second dummy line part (Feng: width of line portion 162a of dummy bit line 160, similar to left 140ST_1 of Chang) in the first direction (horizontal).
Feng, Young and Chang are considered to be analogous to the claimed invention because they are in the same field of memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have more bit line as dummy line with different width as taught by Feng.
Doing so would realize a method to form dummy lines with the bit lines more precisely, and the process yield is improved (Feng: col. 7, lin. 30-33).
Regarding claim 10, Chang in view of Young teaches the semiconductor device of claim 9 including the inner dummy spacer (Young: fig. 5, SP)
Chang in view of Young fails to explicitly teach a length of each of the first parts of the inner dummy spacer in the first direction is less than a length of each of the second parts of the inner dummy spacer in the second direction.
However, Feng teaches a length of each of the first parts of the inner dummy spacer (Young: fig. 5, SP along vertical connect of top and bottom dBL) in the first direction (Feng: annotated fig. 6A, horizontal, perpendicular to line portion 162 of dummy bit line 160; col. 6, lin. 2-4, similar to dBL of Young) is less than (Feng: horizontal direction is less than the vertical direction as shown the dash line rectangle) a length of each of the second parts of the inner dummy spacer (Young: SP along dBL) in the second direction (Feng: vertical, along 162).
Feng, Young and Chang are considered to be analogous to the claimed invention because they are in the same field of memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have more bit line and dummy linewith different width and then the inner dummy spacer with different length as taught by Feng.
Doing so would realize a method to form dummy lines with the bit lines more precisely, and the process yield is improved (Feng: col. 7, lin. 30-33).
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671
582
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(annotated fig. 6A of Feng)
Regarding claim 16, Chang in view of Young teaches the semiconductor device of claim 15, further comprising a dummy dielectric pattern (fig. 7, first cell insulating film 131 under dummy bit line structure 140ST_1; para. 0063) that are on the gate structure (110), wherein:
a bottom surface of dummy line (bottom surface of 140ST_1) contacts a top surface of the dummy dielectric pattern (top surface of 131).
Chang fails to teach the dummy dielectric layer extends into the dummy dielectric pattern and contacts the gate structure.
However, Feng teaches the dummy dielectric layer (Feng: fig. 6A, insulating material 168 between line portion 162 of dummy bit line 160; col. 6, lin. 2-4, similar to Chang: cell line spacer 154 between 140ST_1 and 140ST; para. 0067) extends into the dummy dielectric pattern (Chang: 131) and contacts the gate structure (Chang: 100).
Feng, Young and Chang are considered to be analogous to the claimed invention because they are in the same field of memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have more bit line as dummy line as taught by Feng.
Doing so would realize a method to form dummy lines with the bit lines more precisely, and the process yield is improved (Feng: col. 7, lin. 30-33).
Regarding claim 17, Chang in view of Young and Feng teaches the semiconductor device of claim 16, wherein a bottom surface of the first outer dummy spacer (Chang: fig. 7, 151 on the right side of left 140ST, which is a dummy line as taught ny Feng), a bottom surface of the second outer dummy spacer (Chang: 246_2), and a bottom surface of the inner dummy spacer (Chang: 151 between 140ST_1 and 140ST) contact the top surface of the dummy dielectric pattern (Chang: 131).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Feng.
Regarding claim 18, Chang teaches a semiconductor device (Abstract), comprising:
a substrate (fig. 2, substrate 100; para. 0032);
an active pattern (fig. 3, cell active region ACT; para. 0032) on the substrate (100);
a device isolation layer (fig. 2, cell region isolation film 22; para. 0030) that at least partially surrounds the active pattern (ACT in cell region 20; para. 0030);
a gate structure (fig. 7, cell gate structures 110; para. 0042) that extends in a first direction (first direction D1; para. 0041) on the active pattern (ACT);
a dielectric pattern (first cell insulating film 131; para. 0063) and a dummy dielectric pattern (131 under dummy bit line structure 140ST_1; para. 0071) that are on the gate structure (110);
a bit line (bit line structures 140ST; para. 0042) that extends in a second direction (second direction D2; para. 0041) on the dielectric pattern (131), the second direction (D2) intersecting the first direction (D1);
a gate contact (cell gate contact plug 262; para. 0124) electrically connected to the gate structure (110);
a dummy line (140ST_1) on the dummy dielectric pattern (131) and between the gate contact (262) and the bit line (140ST);
a bit-line contact (146) that electrically connects the bit line (140ST) and the active pattern (ACT) to each other;
a node contact (buried contact BC; para. 0037) electrically connected to the active pattern (ACT);
a landing pad (landing pad LP; para. 0037) electrically connected to the node contact (BC).
Chang fails to teach an inner dummy spacer at least partially surrounded by the dummy line; and
a dummy dielectric layer at least partially surrounded by the inner dummy spacer,
wherein a bottom surface of the inner dummy spacer contacts a top surface of the dummy dielectric pattern, and
wherein the dummy dielectric layer extends into the dummy dielectric pattern and contacts the gate structure.
However, Feng teaches an inner dummy spacer (Feng: fig. 8, spacer 166, col. 6, lin. 54) at least partially surrounded (Feng: fig. 7A, partially surrounded by line portion 162; col. 6, lin. 2) by the dummy line (Feng: dummy bit line 160; col. 6, lin. 4, similar to 140ST_1 and left 140ST of Chang); and
a dummy dielectric layer (Feng: insulating material 168; col. 7, lin. 11) at least partially surrounded by the inner dummy spacer (Feng: 166),
wherein a bottom surface of the inner dummy spacer (Feng: bottom surface of 166) contacts a top surface of the dummy dielectric pattern (Feng: 116; col. 4, lin. 15, similar to 131 of Chang), and
wherein the dummy dielectric layer (Chang: cell line spacer 154 between 140ST_1 and 140ST; para. 0067, similar to 168 of Feng) extends into the dummy dielectric pattern (Chang: 131, similar to 116 of Feng) and contacts the gate structure (Chang: 100).
Feng and Chang are considered to be analogous to the claimed invention because they are in the same field of memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add more bit line as dummy line as taught by Feng.
Doing so would realize a method to form dummy lines with the bit lines more precisely, and the process yield is improved (Feng: col. 7, lin. 30-33).
Regarding claim 19, Chang in view of Feng further teaches the semiconductor device of claim 18, wherein the dummy dielectric pattern (Feng: Feng: fig. 7A, 8, 116 under 162) at least partially surrounds the dummy dielectric layer (Feng: 168).
Regarding claim 20, Chang in view of Feng further teaches the semiconductor device of claim 18, further comprising a dummy line capping layer (Chang: fig. 7, cell line capping film 144; para. 0071) on the dummy line (Chang: 140ST_1 and left 140ST), wherein the dummy line capping layer (Chang: 144 on 160 of Feng) at least partially surrounds the dummy dielectric layer (Feng: 168) and the inner dummy spacer (Feng: 166).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818
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